3785c1d055
Due to some complications with lifetime, and assume-like intrinsics, intrinsics were not included as outlinable instructions. This patch opens up most intrinsics, excluding lifetime and assume-like intrinsics, to be outlined. For similarity, it is required that the intrinsic IDs, and the intrinsics names match exactly, as well as the function type. This puts intrinsics in a different class than normal call instructions (https://reviews.llvm.org/D109448), where the name will no longer have to match. This also adds an additional command line flag debug option to disable outlining intrinsics. Recommit of: 8de76bd569732acae6a10fdcb0152a49f7d4cd39 Adds extra checking of intrinsic function calls names to avoid taking the address of intrinsic calls when extracting function calls. Reviewers: paquette, jroelofs Differential Revision: https://reviews.llvm.org/D109450
88 lines
3.8 KiB
LLVM
88 lines
3.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt -S -verify -iroutliner -ir-outlining-no-cost -no-ir-sim-intrinsics < %s | FileCheck %s
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; This test ensures that we do not outline vararg instructions or intrinsics, as
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; they may cause inconsistencies when outlining.
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declare void @llvm.va_start(i8*)
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declare void @llvm.va_copy(i8*, i8*)
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declare void @llvm.va_end(i8*)
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define i32 @func1(i32 %a, double %b, i8* %v, ...) nounwind {
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; CHECK-LABEL: @func1(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[AP1_LOC:%.*]] = alloca i8*, align 8
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; CHECK-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
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; CHECK-NEXT: [[B_ADDR:%.*]] = alloca double, align 8
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; CHECK-NEXT: [[AP:%.*]] = alloca i8*, align 4
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; CHECK-NEXT: [[C:%.*]] = alloca i32, align 4
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; CHECK-NEXT: [[LT_CAST:%.*]] = bitcast i8** [[AP1_LOC]] to i8*
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; CHECK-NEXT: call void @llvm.lifetime.start.p0i8(i64 -1, i8* [[LT_CAST]])
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; CHECK-NEXT: call void @outlined_ir_func_0(i32 [[A:%.*]], i32* [[A_ADDR]], double [[B:%.*]], double* [[B_ADDR]], i8** [[AP]], i8** [[AP1_LOC]])
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; CHECK-NEXT: [[AP1_RELOAD:%.*]] = load i8*, i8** [[AP1_LOC]], align 8
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; CHECK-NEXT: call void @llvm.lifetime.end.p0i8(i64 -1, i8* [[LT_CAST]])
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; CHECK-NEXT: call void @llvm.va_start(i8* [[AP1_RELOAD]])
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; CHECK-NEXT: [[TMP0:%.*]] = va_arg i8** [[AP]], i32
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; CHECK-NEXT: call void @llvm.va_copy(i8* [[V:%.*]], i8* [[AP1_RELOAD]])
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; CHECK-NEXT: call void @llvm.va_end(i8* [[AP1_RELOAD]])
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; CHECK-NEXT: store i32 [[TMP0]], i32* [[C]], align 4
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; CHECK-NEXT: [[TMP:%.*]] = load i32, i32* [[C]], align 4
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; CHECK-NEXT: ret i32 [[TMP]]
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;
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entry:
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%a.addr = alloca i32, align 4
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%b.addr = alloca double, align 8
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%ap = alloca i8*, align 4
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%c = alloca i32, align 4
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store i32 %a, i32* %a.addr, align 4
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store double %b, double* %b.addr, align 8
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%ap1 = bitcast i8** %ap to i8*
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call void @llvm.va_start(i8* %ap1)
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%0 = va_arg i8** %ap, i32
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call void @llvm.va_copy(i8* %v, i8* %ap1)
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call void @llvm.va_end(i8* %ap1)
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store i32 %0, i32* %c, align 4
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%tmp = load i32, i32* %c, align 4
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ret i32 %tmp
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}
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define i32 @func2(i32 %a, double %b, i8* %v, ...) nounwind {
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; CHECK-LABEL: @func2(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[AP1_LOC:%.*]] = alloca i8*, align 8
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; CHECK-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
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; CHECK-NEXT: [[B_ADDR:%.*]] = alloca double, align 8
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; CHECK-NEXT: [[AP:%.*]] = alloca i8*, align 4
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; CHECK-NEXT: [[C:%.*]] = alloca i32, align 4
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; CHECK-NEXT: [[LT_CAST:%.*]] = bitcast i8** [[AP1_LOC]] to i8*
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; CHECK-NEXT: call void @llvm.lifetime.start.p0i8(i64 -1, i8* [[LT_CAST]])
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; CHECK-NEXT: call void @outlined_ir_func_0(i32 [[A:%.*]], i32* [[A_ADDR]], double [[B:%.*]], double* [[B_ADDR]], i8** [[AP]], i8** [[AP1_LOC]])
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; CHECK-NEXT: [[AP1_RELOAD:%.*]] = load i8*, i8** [[AP1_LOC]], align 8
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; CHECK-NEXT: call void @llvm.lifetime.end.p0i8(i64 -1, i8* [[LT_CAST]])
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; CHECK-NEXT: call void @llvm.va_start(i8* [[AP1_RELOAD]])
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; CHECK-NEXT: [[TMP0:%.*]] = va_arg i8** [[AP]], i32
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; CHECK-NEXT: call void @llvm.va_copy(i8* [[V:%.*]], i8* [[AP1_RELOAD]])
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; CHECK-NEXT: call void @llvm.va_end(i8* [[AP1_RELOAD]])
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; CHECK-NEXT: store i32 [[TMP0]], i32* [[C]], align 4
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; CHECK-NEXT: [[AP2:%.*]] = bitcast i8** [[AP]] to i8*
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; CHECK-NEXT: [[TMP:%.*]] = load i32, i32* [[C]], align 4
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; CHECK-NEXT: ret i32 [[TMP]]
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;
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entry:
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%a.addr = alloca i32, align 4
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%b.addr = alloca double, align 8
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%ap = alloca i8*, align 4
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%c = alloca i32, align 4
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store i32 %a, i32* %a.addr, align 4
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store double %b, double* %b.addr, align 8
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%ap1 = bitcast i8** %ap to i8*
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call void @llvm.va_start(i8* %ap1)
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%0 = va_arg i8** %ap, i32
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call void @llvm.va_copy(i8* %v, i8* %ap1)
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call void @llvm.va_end(i8* %ap1)
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store i32 %0, i32* %c, align 4
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%ap2 = bitcast i8** %ap to i8*
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%tmp = load i32, i32* %c, align 4
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ret i32 %tmp
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}
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