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llvm-project/llvm/test/Transforms/IndVarSimplify/ashr-expansion.ll
Philip Reames 8906a0fe64 [SCEVExpander] Drop poison generating flags when reusing instructions 
The basic problem we have is that we're trying to reuse an instruction which is mapped to some SCEV. Since we can have multiple such instructions (potentially with different flags), this is analogous to our need to drop flags when performing CSE. A trivial implementation would simply drop flags on any instruction we decided to reuse, and that would be correct.

This patch is almost that trivial patch except that we preserve flags on the reused instruction when existing users would imply UB on overflow already. Adding new users can, at most, refine this program to one which doesn't execute UB which is valid.

In practice, this fixes two conceptual problems with the previous code: 1) a binop could have been canonicalized into a form with different opcode or operands, or 2) the inbounds GEP case which was simply unhandled.

On the test changes, most are pretty straight forward. We loose some flags (in some cases, they'd have been dropped on the next CSE pass anyways). The one that took me the longest to understand was the ashr-expansion test. What's happening there is that we're considering reuse of the mul, previously we disallowed it entirely, now we allow it with no flags. The surrounding diffs are all effects of generating the same mul with a different operand order, and then doing simple DCE.

The loss of the inbounds is unfortunate, but even there, we can recover most of those once we actually treat branch-on-poison as immediate UB.

Differential Revision: https://reviews.llvm.org/D112734
2021-11-29 15:23:34 -08:00

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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt -indvars -S %s | FileCheck %s
target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
define float @ashr_expansion_valid(i64 %x, float* %ptr) {
; CHECK-LABEL: @ashr_expansion_valid(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[BOUND:%.*]] = ashr i64 [[X:%.*]], 4
; CHECK-NEXT: [[UMAX:%.*]] = call i64 @llvm.umax.i64(i64 [[BOUND]], i64 1)
; CHECK-NEXT: br label [[LOOP:%.*]]
; CHECK: loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ]
; CHECK-NEXT: [[RED:%.*]] = phi float [ 0.000000e+00, [[ENTRY]] ], [ [[RED_NEXT:%.*]], [[LOOP]] ]
; CHECK-NEXT: [[GEP:%.*]] = getelementptr float, float* [[PTR:%.*]], i64 [[IV]]
; CHECK-NEXT: [[LV:%.*]] = load float, float* [[GEP]], align 4
; CHECK-NEXT: [[RED_NEXT]] = fadd float [[LV]], [[RED]]
; CHECK-NEXT: [[IV_NEXT]] = add nuw i64 [[IV]], 1
; CHECK-NEXT: [[EXITCOND:%.*]] = icmp ne i64 [[IV_NEXT]], [[UMAX]]
; CHECK-NEXT: br i1 [[EXITCOND]], label [[LOOP]], label [[EXIT:%.*]]
; CHECK: exit:
; CHECK-NEXT: [[LCSSA_RED_NEXT:%.*]] = phi float [ [[RED_NEXT]], [[LOOP]] ]
; CHECK-NEXT: ret float [[LCSSA_RED_NEXT]]
;
entry:
%bound = ashr exact i64 %x, 4
br label %loop
loop:
%iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
%red = phi float [ 0.0, %entry ], [ %red.next, %loop ]
%gep = getelementptr float, float* %ptr, i64 %iv
%lv = load float, float* %gep
%red.next = fadd float %lv, %red
%iv.next = add nuw i64 %iv, 1
%cond = icmp ult i64 %iv.next, %bound
br i1 %cond, label %loop, label %exit
exit: ; preds = %bb135
%lcssa.red.next = phi float [ %red.next, %loop ]
ret float %lcssa.red.next
}
; No explicit ashr, but a chain of operations that can be replaced by ashr.
define float @ashr_equivalent_expansion(i64 %x, float* %ptr) {
; CHECK-LABEL: @ashr_equivalent_expansion(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[ABS_X:%.*]] = call i64 @llvm.abs.i64(i64 [[X:%.*]], i1 false)
; CHECK-NEXT: [[DIV:%.*]] = udiv exact i64 [[ABS_X]], 16
; CHECK-NEXT: [[T0:%.*]] = call i64 @llvm.smax.i64(i64 [[X]], i64 -1)
; CHECK-NEXT: [[T1:%.*]] = call i64 @llvm.smin.i64(i64 [[T0]], i64 1)
; CHECK-NEXT: [[BOUND:%.*]] = mul i64 [[DIV]], [[T1]]
; CHECK-NEXT: [[UMAX:%.*]] = call i64 @llvm.umax.i64(i64 [[BOUND]], i64 1)
; CHECK-NEXT: br label [[LOOP:%.*]]
; CHECK: loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ]
; CHECK-NEXT: [[RED:%.*]] = phi float [ 0.000000e+00, [[ENTRY]] ], [ [[RED_NEXT:%.*]], [[LOOP]] ]
; CHECK-NEXT: [[GEP:%.*]] = getelementptr float, float* [[PTR:%.*]], i64 [[IV]]
; CHECK-NEXT: [[LV:%.*]] = load float, float* [[GEP]], align 4
; CHECK-NEXT: [[RED_NEXT]] = fadd float [[LV]], [[RED]]
; CHECK-NEXT: [[IV_NEXT]] = add nuw i64 [[IV]], 1
; CHECK-NEXT: [[EXITCOND:%.*]] = icmp ne i64 [[IV_NEXT]], [[UMAX]]
; CHECK-NEXT: br i1 [[EXITCOND]], label [[LOOP]], label [[EXIT:%.*]]
; CHECK: exit:
; CHECK-NEXT: [[LCSSA_RED_NEXT:%.*]] = phi float [ [[RED_NEXT]], [[LOOP]] ]
; CHECK-NEXT: ret float [[LCSSA_RED_NEXT]]
;
entry:
%abs_x = call i64 @llvm.abs.i64(i64 %x, i1 false)
%div = udiv exact i64 %abs_x, 16
%t0 = call i64 @llvm.smax.i64(i64 %x, i64 -1)
%t1 = call i64 @llvm.smin.i64(i64 %t0, i64 1)
%bound = mul nsw i64 %div, %t1
br label %loop
loop:
%iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
%red = phi float [ 0.0, %entry ], [ %red.next, %loop ]
%gep = getelementptr float, float* %ptr, i64 %iv
%lv = load float, float* %gep
%red.next = fadd float %lv, %red
%iv.next = add nuw i64 %iv, 1
%cond = icmp ult i64 %iv.next, %bound
br i1 %cond, label %loop, label %exit
exit: ; preds = %bb135
%lcssa.red.next = phi float [ %red.next, %loop ]
ret float %lcssa.red.next
}
; Chain of operations that *cannot* be replaced by ashr, because the udiv is
; missing exact.
define float @no_ashr_due_to_missing_exact_udiv(i64 %x, float* %ptr) {
; CHECK-LABEL: @no_ashr_due_to_missing_exact_udiv(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[ABS_X:%.*]] = call i64 @llvm.abs.i64(i64 [[X:%.*]], i1 false)
; CHECK-NEXT: [[DIV:%.*]] = udiv i64 [[ABS_X]], 16
; CHECK-NEXT: [[T0:%.*]] = call i64 @llvm.smax.i64(i64 [[X]], i64 -1)
; CHECK-NEXT: [[T1:%.*]] = call i64 @llvm.smin.i64(i64 [[T0]], i64 1)
; CHECK-NEXT: [[BOUND:%.*]] = mul i64 [[DIV]], [[T1]]
; CHECK-NEXT: [[UMAX:%.*]] = call i64 @llvm.umax.i64(i64 [[BOUND]], i64 1)
; CHECK-NEXT: br label [[LOOP:%.*]]
; CHECK: loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ]
; CHECK-NEXT: [[RED:%.*]] = phi float [ 0.000000e+00, [[ENTRY]] ], [ [[RED_NEXT:%.*]], [[LOOP]] ]
; CHECK-NEXT: [[GEP:%.*]] = getelementptr float, float* [[PTR:%.*]], i64 [[IV]]
; CHECK-NEXT: [[LV:%.*]] = load float, float* [[GEP]], align 4
; CHECK-NEXT: [[RED_NEXT]] = fadd float [[LV]], [[RED]]
; CHECK-NEXT: [[IV_NEXT]] = add nuw i64 [[IV]], 1
; CHECK-NEXT: [[EXITCOND:%.*]] = icmp ne i64 [[IV_NEXT]], [[UMAX]]
; CHECK-NEXT: br i1 [[EXITCOND]], label [[LOOP]], label [[EXIT:%.*]]
; CHECK: exit:
; CHECK-NEXT: [[LCSSA_RED_NEXT:%.*]] = phi float [ [[RED_NEXT]], [[LOOP]] ]
; CHECK-NEXT: ret float [[LCSSA_RED_NEXT]]
;
entry:
%abs_x = call i64 @llvm.abs.i64(i64 %x, i1 false)
%div = udiv i64 %abs_x, 16
%t0 = call i64 @llvm.smax.i64(i64 %x, i64 -1)
%t1 = call i64 @llvm.smin.i64(i64 %t0, i64 1)
%bound = mul nsw i64 %div, %t1
br label %loop
loop:
%iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
%red = phi float [ 0.0, %entry ], [ %red.next, %loop ]
%gep = getelementptr float, float* %ptr, i64 %iv
%lv = load float, float* %gep
%red.next = fadd float %lv, %red
%iv.next = add nuw i64 %iv, 1
%cond = icmp ult i64 %iv.next, %bound
br i1 %cond, label %loop, label %exit
exit: ; preds = %bb135
%lcssa.red.next = phi float [ %red.next, %loop ]
ret float %lcssa.red.next
}
; Chain of operations that *cannot* be replaced by ashr, because abs and
; signum have different operands.
define float @no_ashr_due_to_different_ops(i64 %x, i64 %y, float* %ptr) {
; CHECK-LABEL: @no_ashr_due_to_different_ops(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[ABS_X:%.*]] = call i64 @llvm.abs.i64(i64 [[X:%.*]], i1 false)
; CHECK-NEXT: [[DIV:%.*]] = udiv i64 [[ABS_X]], 16
; CHECK-NEXT: [[T0:%.*]] = call i64 @llvm.smax.i64(i64 [[Y:%.*]], i64 -1)
; CHECK-NEXT: [[T1:%.*]] = call i64 @llvm.smin.i64(i64 [[T0]], i64 1)
; CHECK-NEXT: [[BOUND:%.*]] = mul i64 [[DIV]], [[T1]]
; CHECK-NEXT: [[UMAX:%.*]] = call i64 @llvm.umax.i64(i64 [[BOUND]], i64 1)
; CHECK-NEXT: br label [[LOOP:%.*]]
; CHECK: loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ]
; CHECK-NEXT: [[RED:%.*]] = phi float [ 0.000000e+00, [[ENTRY]] ], [ [[RED_NEXT:%.*]], [[LOOP]] ]
; CHECK-NEXT: [[GEP:%.*]] = getelementptr float, float* [[PTR:%.*]], i64 [[IV]]
; CHECK-NEXT: [[LV:%.*]] = load float, float* [[GEP]], align 4
; CHECK-NEXT: [[RED_NEXT]] = fadd float [[LV]], [[RED]]
; CHECK-NEXT: [[IV_NEXT]] = add nuw i64 [[IV]], 1
; CHECK-NEXT: [[EXITCOND:%.*]] = icmp ne i64 [[IV_NEXT]], [[UMAX]]
; CHECK-NEXT: br i1 [[EXITCOND]], label [[LOOP]], label [[EXIT:%.*]]
; CHECK: exit:
; CHECK-NEXT: [[LCSSA_RED_NEXT:%.*]] = phi float [ [[RED_NEXT]], [[LOOP]] ]
; CHECK-NEXT: ret float [[LCSSA_RED_NEXT]]
;
entry:
%abs_x = call i64 @llvm.abs.i64(i64 %x, i1 false)
%div = udiv i64 %abs_x, 16
%t0 = call i64 @llvm.smax.i64(i64 %y, i64 -1)
%t1 = call i64 @llvm.smin.i64(i64 %t0, i64 1)
%bound = mul nsw i64 %div, %t1
br label %loop
loop:
%iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
%red = phi float [ 0.0, %entry ], [ %red.next, %loop ]
%gep = getelementptr float, float* %ptr, i64 %iv
%lv = load float, float* %gep
%red.next = fadd float %lv, %red
%iv.next = add nuw i64 %iv, 1
%cond = icmp ult i64 %iv.next, %bound
br i1 %cond, label %loop, label %exit
exit: ; preds = %bb135
%lcssa.red.next = phi float [ %red.next, %loop ]
ret float %lcssa.red.next
}
declare i64 @llvm.abs.i64(i64, i1)
declare i64 @llvm.smax.i64(i64, i64)
declare i64 @llvm.smin.i64(i64, i64)
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