This patch fixes a logical error in how we work with `LoopUsers` map.
It maps a loop onto a set of AddRecs that depend on it. The Addrecs
are added to this map only once when they are created and put to
the UniqueSCEVs` map.
The only purpose of this map is to make sure that, whenever we forget
a loop, all (directly or indirectly) dependent SCEVs get forgotten too.
Current code erases SCEVs from dependent set of a given loop whenever
we forget this loop. This is not a correct behavior due to the following scenario:
1. We have a loop `L` and an AddRec `AR` that depends on it;
2. We modify something in the loop, but don't destroy it. We still call forgetLoop on it;
3. `AR` is no longer dependent on `L` according to `LoopUsers`. It is erased from
ValueExprMap` and `ExprValue map, but still exists in UniqueSCEVs;
4. We can later request the very same AddRec for the very same loop again, and get existing
SCEV `AR`.
5. Now, `AR` exists and is used again, but its notion that it depends on `L` is lost;
6. Then we decide to delete `L`. `AR` will not be forgotten because we have lost it;
7. Just you wait when you run into a dangling pointer problem, or any other kind of problem
because an active SCEV is now referecing a non-existent loop.
The solution to this is to stop erasing values from `LoopUsers`. Yes, we will maybe forget something
that is already not used, but it's cheap.
This fixes a functional bug and potentially may have negative compile time impact on methods with
huge or numerous loops.
Differential Revision: https://reviews.llvm.org/D120303
Reviewed By: nikic
140 lines
5.4 KiB
LLVM
140 lines
5.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt -passes="loop(indvars,loop-deletion)" -S < %s | FileCheck %s
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target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128-ni:1-p2:32:8:8:32-ni:2"
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target triple = "x86_64-unknown-linux-gnu"
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; Make sure we don't crash.
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define void @test() {
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; CHECK-LABEL: @test(
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; CHECK-NEXT: bb:
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; CHECK-NEXT: br label [[BB1:%.*]]
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; CHECK: bb1:
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; CHECK-NEXT: [[TMP2:%.*]] = phi i32 [ 11, [[BB:%.*]] ]
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; CHECK-NEXT: [[TMP3:%.*]] = add nsw i32 112, -1
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; CHECK-NEXT: [[TMP4:%.*]] = add nuw nsw i32 [[TMP2]], 1
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; CHECK-NEXT: [[TMP5:%.*]] = mul i32 [[TMP3]], [[TMP3]]
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; CHECK-NEXT: [[TMP6:%.*]] = mul nsw i32 [[TMP2]], -6
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; CHECK-NEXT: [[TMP7:%.*]] = mul nsw i32 [[TMP6]], [[TMP5]]
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; CHECK-NEXT: [[TMP8:%.*]] = add nuw nsw i32 [[TMP7]], [[TMP2]]
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; CHECK-NEXT: [[TMP9:%.*]] = and i32 undef, 1
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; CHECK-NEXT: [[TMP10:%.*]] = icmp eq i32 [[TMP9]], 0
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; CHECK-NEXT: br i1 [[TMP10]], label [[BB33_LOOPEXIT1:%.*]], label [[BB34_PREHEADER:%.*]]
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; CHECK: bb34.preheader:
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; CHECK-NEXT: br label [[BB34:%.*]]
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; CHECK: bb11:
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; CHECK-NEXT: [[TMP2_LCSSA12:%.*]] = phi i32 [ 11, [[BB34]] ]
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; CHECK-NEXT: br label [[BB33_LOOPEXIT:%.*]]
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; CHECK: bb12:
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; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[TMP40:%.*]], 0
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; CHECK-NEXT: br label [[BB14:%.*]]
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; CHECK: bb14:
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; CHECK-NEXT: br i1 true, label [[BB32:%.*]], label [[BB22:%.*]]
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; CHECK: bb22:
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; CHECK-NEXT: [[TMP1:%.*]] = trunc i64 4 to i32
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; CHECK-NEXT: [[TMP23:%.*]] = or i32 [[TMP1]], undef
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; CHECK-NEXT: [[TMP24:%.*]] = add i32 [[TMP23]], undef
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; CHECK-NEXT: br i1 false, label [[BB42:%.*]], label [[BB25:%.*]]
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; CHECK: bb25:
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; CHECK-NEXT: br label [[BB31:%.*]]
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; CHECK: bb31:
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; CHECK-NEXT: unreachable
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; CHECK: bb32:
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; CHECK-NEXT: ret void
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; CHECK: bb33.loopexit:
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; CHECK-NEXT: [[TMP2_LCSSA9:%.*]] = phi i32 [ [[TMP2_LCSSA12]], [[BB11:%.*]] ]
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; CHECK-NEXT: br label [[BB33:%.*]]
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; CHECK: bb33.loopexit1:
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; CHECK-NEXT: [[TMP2_LCSSA:%.*]] = phi i32 [ [[TMP2]], [[BB1]] ]
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; CHECK-NEXT: br label [[BB33]]
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; CHECK: bb33:
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; CHECK-NEXT: [[TMP210:%.*]] = phi i32 [ [[TMP2_LCSSA]], [[BB33_LOOPEXIT1]] ], [ [[TMP2_LCSSA9]], [[BB33_LOOPEXIT]] ]
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; CHECK-NEXT: call void @use(i32 [[TMP210]])
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; CHECK-NEXT: ret void
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; CHECK: bb34:
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; CHECK-NEXT: [[TMP36:%.*]] = xor i32 0, [[TMP8]]
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; CHECK-NEXT: [[TMP38:%.*]] = add i32 [[TMP36]], undef
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; CHECK-NEXT: [[TMP39:%.*]] = add i32 [[TMP38]], undef
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; CHECK-NEXT: [[TMP40]] = sext i32 [[TMP39]] to i64
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; CHECK-NEXT: br i1 false, label [[BB11]], label [[BB12:%.*]]
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; CHECK: bb42:
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; CHECK-NEXT: [[TMP24_LCSSA:%.*]] = phi i32 [ [[TMP24]], [[BB22]] ]
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; CHECK-NEXT: [[TMP18_LCSSA4:%.*]] = phi i64 [ [[TMP0]], [[BB22]] ]
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; CHECK-NEXT: store atomic i64 [[TMP18_LCSSA4]], i64 addrspace(1)* undef unordered, align 8
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; CHECK-NEXT: call void @use(i32 [[TMP24_LCSSA]])
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; CHECK-NEXT: ret void
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;
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bb:
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br label %bb1
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bb1: ; preds = %bb31, %bb
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%tmp = phi i32 [ %tmp29, %bb31 ], [ undef, %bb ]
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%tmp2 = phi i32 [ %tmp4, %bb31 ], [ 11, %bb ]
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%tmp3 = add nsw i32 112, -1
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%tmp4 = add nuw nsw i32 %tmp2, 1
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%tmp5 = mul i32 %tmp3, %tmp3
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%tmp6 = mul nsw i32 %tmp2, -6
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%tmp7 = mul i32 %tmp6, %tmp5
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%tmp8 = add i32 %tmp7, %tmp2
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%tmp9 = and i32 undef, 1
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%tmp10 = icmp eq i32 %tmp9, 0
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br i1 %tmp10, label %bb33, label %bb34
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bb11: ; preds = %bb34
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br i1 undef, label %bb33, label %bb34
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bb12: ; preds = %bb34
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%tmp13 = icmp eq i8 addrspace(1)* undef, null
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br label %bb14
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bb14: ; preds = %bb25, %bb12
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%tmp15 = phi i32 [ %tmp29, %bb25 ], [ %tmp37, %bb12 ]
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%tmp16 = phi i64 [ undef, %bb25 ], [ %tmp41, %bb12 ]
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%tmp17 = phi i32 [ %tmp26, %bb25 ], [ 4, %bb12 ]
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%tmp18 = add i64 %tmp16, undef
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%tmp19 = add i32 %tmp15, 1
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%tmp20 = and i32 %tmp19, 1
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%tmp21 = icmp eq i32 %tmp20, 0
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br i1 %tmp21, label %bb32, label %bb22
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bb22: ; preds = %bb14
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%tmp23 = or i32 %tmp17, undef
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%tmp24 = add i32 %tmp23, undef
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br i1 %tmp13, label %bb42, label %bb25
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bb25: ; preds = %bb22
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%tmp26 = add nuw nsw i32 %tmp17, 1
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%tmp27 = zext i32 %tmp26 to i64
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%tmp28 = getelementptr inbounds i32, i32 addrspace(1)* undef, i64 %tmp27
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%tmp29 = add i32 %tmp15, 3
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%tmp30 = icmp ugt i32 %tmp17, 110
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br i1 %tmp30, label %bb31, label %bb14
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bb31: ; preds = %bb25
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br label %bb1
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bb32: ; preds = %bb14
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ret void
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bb33: ; preds = %bb11, %bb1
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call void @use(i32 %tmp2)
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ret void
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bb34: ; preds = %bb11, %bb1
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%tmp35 = phi i32 [ %tmp37, %bb11 ], [ %tmp, %bb1 ]
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%tmp36 = xor i32 0, %tmp8
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%tmp37 = add i32 %tmp35, 2
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%tmp38 = add i32 %tmp36, undef
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%tmp39 = add i32 %tmp38, undef
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%tmp40 = sext i32 %tmp39 to i64
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%tmp41 = add i64 undef, %tmp40
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br i1 undef, label %bb11, label %bb12
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bb42: ; preds = %bb22
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store atomic i64 %tmp18, i64 addrspace(1)* undef unordered, align 8
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call void @use(i32 %tmp24)
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ret void
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}
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declare void @use(i32)
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