de2fed6152
The unrolling code was previously inserting new cloned blocks at the end of the function. The result of this with typical loop structures is that the new iterations are placed far from the initial iteration. With unrolling, the general assumption is that the a) the loop is reasonable hot, and b) the first Count-1 copies of the loop are rarely (if ever) loop exiting. As such, placing Count-1 copies out of line is a fairly poor code placement choice. We'd much rather fall through into the hot (non-exiting) path. For code with branch profiles, later layout would fix this, but this may have a positive impact on non-PGO compiled code. However, the real motivation for this change isn't performance. Its readability and human understanding. Having to jump around long distances in an IR file to trace an unrolled loop structure is error prone and tedious.
105 lines
4.7 KiB
LLVM
105 lines
4.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt < %s -loop-unroll -unroll-count=2 -S | FileCheck %s
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; LoopUnroll should unroll this loop into one big basic block.
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define void @latch_exit(double* nocapture %p, i64 %n) nounwind {
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; CHECK-LABEL: @latch_exit(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[MUL10:%.*]] = shl i64 [[N:%.*]], 1
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; CHECK-NEXT: br label [[FOR_BODY:%.*]]
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; CHECK: for.body:
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; CHECK-NEXT: [[I_013:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[TMP16_1:%.*]], [[FOR_BODY]] ]
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; CHECK-NEXT: [[ARRAYIDX7:%.*]] = getelementptr double, double* [[P:%.*]], i64 [[I_013]]
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; CHECK-NEXT: [[TMP16:%.*]] = add nuw nsw i64 [[I_013]], 1
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; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr double, double* [[P]], i64 [[TMP16]]
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; CHECK-NEXT: [[TMP4:%.*]] = load double, double* [[ARRAYIDX]], align 8
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; CHECK-NEXT: [[TMP8:%.*]] = load double, double* [[ARRAYIDX7]], align 8
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; CHECK-NEXT: [[MUL9:%.*]] = fmul double [[TMP8]], [[TMP4]]
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; CHECK-NEXT: store double [[MUL9]], double* [[ARRAYIDX7]], align 8
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; CHECK-NEXT: [[ARRAYIDX7_1:%.*]] = getelementptr double, double* [[P]], i64 [[TMP16]]
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; CHECK-NEXT: [[TMP16_1]] = add i64 [[TMP16]], 1
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; CHECK-NEXT: [[ARRAYIDX_1:%.*]] = getelementptr double, double* [[P]], i64 [[TMP16_1]]
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; CHECK-NEXT: [[TMP4_1:%.*]] = load double, double* [[ARRAYIDX_1]], align 8
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; CHECK-NEXT: [[TMP8_1:%.*]] = load double, double* [[ARRAYIDX7_1]], align 8
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; CHECK-NEXT: [[MUL9_1:%.*]] = fmul double [[TMP8_1]], [[TMP4_1]]
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; CHECK-NEXT: store double [[MUL9_1]], double* [[ARRAYIDX7_1]], align 8
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; CHECK-NEXT: [[EXITCOND_1:%.*]] = icmp eq i64 [[TMP16_1]], [[MUL10]]
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; CHECK-NEXT: br i1 [[EXITCOND_1]], label [[FOR_END:%.*]], label [[FOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
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; CHECK: for.end:
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; CHECK-NEXT: ret void
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;
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entry:
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%mul10 = shl i64 %n, 1
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br label %for.body
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for.body:
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%i.013 = phi i64 [ %tmp16, %for.body ], [ 0, %entry ]
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%arrayidx7 = getelementptr double, double* %p, i64 %i.013
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%tmp16 = add i64 %i.013, 1
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%arrayidx = getelementptr double, double* %p, i64 %tmp16
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%tmp4 = load double, double* %arrayidx
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%tmp8 = load double, double* %arrayidx7
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%mul9 = fmul double %tmp8, %tmp4
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store double %mul9, double* %arrayidx7
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%exitcond = icmp eq i64 %tmp16, %mul10
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br i1 %exitcond, label %for.end, label %for.body
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for.end:
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ret void
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}
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; Same as previous test case, but with a non-latch exit. There shouldn't
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; be a conditional branch after the first block.
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define void @non_latch_exit(double* nocapture %p, i64 %n) nounwind {
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; CHECK-LABEL: @non_latch_exit(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[MUL10:%.*]] = shl i64 [[N:%.*]], 1
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; CHECK-NEXT: br label [[FOR_BODY:%.*]]
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; CHECK: for.body:
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; CHECK-NEXT: [[I_013:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[TMP16_1:%.*]], [[LATCH_1:%.*]] ]
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; CHECK-NEXT: [[ARRAYIDX7:%.*]] = getelementptr double, double* [[P:%.*]], i64 [[I_013]]
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; CHECK-NEXT: [[TMP16:%.*]] = add nuw nsw i64 [[I_013]], 1
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; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr double, double* [[P]], i64 [[TMP16]]
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; CHECK-NEXT: [[TMP4:%.*]] = load double, double* [[ARRAYIDX]], align 8
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; CHECK-NEXT: [[TMP8:%.*]] = load double, double* [[ARRAYIDX7]], align 8
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; CHECK-NEXT: [[MUL9:%.*]] = fmul double [[TMP8]], [[TMP4]]
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; CHECK-NEXT: store double [[MUL9]], double* [[ARRAYIDX7]], align 8
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; CHECK-NEXT: br label [[LATCH:%.*]]
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; CHECK: latch:
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; CHECK-NEXT: [[ARRAYIDX7_1:%.*]] = getelementptr double, double* [[P]], i64 [[TMP16]]
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; CHECK-NEXT: [[TMP16_1]] = add i64 [[TMP16]], 1
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; CHECK-NEXT: [[ARRAYIDX_1:%.*]] = getelementptr double, double* [[P]], i64 [[TMP16_1]]
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; CHECK-NEXT: [[TMP4_1:%.*]] = load double, double* [[ARRAYIDX_1]], align 8
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; CHECK-NEXT: [[TMP8_1:%.*]] = load double, double* [[ARRAYIDX7_1]], align 8
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; CHECK-NEXT: [[MUL9_1:%.*]] = fmul double [[TMP8_1]], [[TMP4_1]]
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; CHECK-NEXT: store double [[MUL9_1]], double* [[ARRAYIDX7_1]], align 8
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; CHECK-NEXT: [[EXITCOND_1:%.*]] = icmp eq i64 [[TMP16_1]], [[MUL10]]
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; CHECK-NEXT: br i1 [[EXITCOND_1]], label [[FOR_END:%.*]], label [[LATCH_1]]
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; CHECK: latch.1:
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; CHECK-NEXT: br label [[FOR_BODY]], !llvm.loop [[LOOP2:![0-9]+]]
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; CHECK: for.end:
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; CHECK-NEXT: ret void
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;
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entry:
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%mul10 = shl i64 %n, 1
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br label %for.body
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for.body:
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%i.013 = phi i64 [ %tmp16, %latch ], [ 0, %entry ]
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%arrayidx7 = getelementptr double, double* %p, i64 %i.013
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%tmp16 = add i64 %i.013, 1
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%arrayidx = getelementptr double, double* %p, i64 %tmp16
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%tmp4 = load double, double* %arrayidx
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%tmp8 = load double, double* %arrayidx7
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%mul9 = fmul double %tmp8, %tmp4
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store double %mul9, double* %arrayidx7
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%exitcond = icmp eq i64 %tmp16, %mul10
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br i1 %exitcond, label %for.end, label %latch
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latch:
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br label %for.body
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for.end:
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ret void
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}
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