ede248e614
If we assume `llvm.amdgcn.s.barrier` is aligned we may remove it and cause OpenMP GPU applications on the AMD GPU to be stuck or wrongly synchronized. Reported by Carlo Bertolli.
266 lines
9.7 KiB
LLVM
266 lines
9.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --check-globals
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; RUN: opt < %s -S -openmp-opt-cgscc | FileCheck %s
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; RUN: opt < %s -S -passes=openmp-opt-cgscc | FileCheck %s
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declare void @useI32(i32)
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declare void @unknown()
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declare void @aligned_barrier() "llvm.assume"="ompx_aligned_barrier"
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declare void @llvm.nvvm.barrier0()
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declare i32 @llvm.nvvm.barrier0.and(i32)
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declare i32 @llvm.nvvm.barrier0.or(i32)
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declare i32 @llvm.nvvm.barrier0.popc(i32)
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declare void @llvm.amdgcn.s.barrier()
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;.
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; CHECK: @[[GC1:[a-zA-Z0-9_$"\\.-]+]] = constant i32 42
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; CHECK: @[[GC2:[a-zA-Z0-9_$"\\.-]+]] = addrspace(4) global i32 0
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; CHECK: @[[GPTR4:[a-zA-Z0-9_$"\\.-]+]] = addrspace(4) global i32 addrspace(4)* null
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; CHECK: @[[G:[a-zA-Z0-9_$"\\.-]+]] = global i32 42
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; CHECK: @[[GS:[a-zA-Z0-9_$"\\.-]+]] = addrspace(3) global i32 0
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; CHECK: @[[GPTR:[a-zA-Z0-9_$"\\.-]+]] = global i32* null
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; CHECK: @[[PG1:[a-zA-Z0-9_$"\\.-]+]] = thread_local global i32 42
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; CHECK: @[[PG2:[a-zA-Z0-9_$"\\.-]+]] = addrspace(5) global i32 0
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; CHECK: @[[GPTR5:[a-zA-Z0-9_$"\\.-]+]] = global i32 addrspace(5)* null
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; CHECK: @[[G1:[a-zA-Z0-9_$"\\.-]+]] = global i32 42
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; CHECK: @[[G2:[a-zA-Z0-9_$"\\.-]+]] = addrspace(1) global i32 0
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;.
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define void @pos_empty_1() {
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; CHECK-LABEL: define {{[^@]+}}@pos_empty_1() {
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; CHECK-NEXT: ret void
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;
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call void @unknown() "llvm.assume"="ompx_aligned_barrier"
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ret void
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}
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define void @pos_empty_2() {
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; CHECK-LABEL: define {{[^@]+}}@pos_empty_2() {
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; CHECK-NEXT: ret void
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;
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call void @aligned_barrier()
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ret void
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}
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define void @pos_empty_3() {
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; CHECK-LABEL: define {{[^@]+}}@pos_empty_3() {
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; CHECK-NEXT: ret void
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;
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call void @llvm.nvvm.barrier0()
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ret void
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}
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define void @pos_empty_4() {
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; CHECK-LABEL: define {{[^@]+}}@pos_empty_4() {
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; CHECK-NEXT: ret void
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;
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call i32 @llvm.nvvm.barrier0.and(i32 0)
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ret void
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}
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define void @pos_empty_5() {
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; CHECK-LABEL: define {{[^@]+}}@pos_empty_5() {
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; CHECK-NEXT: ret void
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;
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call i32 @llvm.nvvm.barrier0.or(i32 0)
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ret void
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}
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define void @pos_empty_6() {
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; CHECK-LABEL: define {{[^@]+}}@pos_empty_6() {
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; CHECK-NEXT: ret void
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;
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call i32 @llvm.nvvm.barrier0.popc(i32 0)
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ret void
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}
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define void @neg_empty_7() {
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; CHECK-LABEL: define {{[^@]+}}@neg_empty_7() {
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; CHECK-NEXT: call void @llvm.amdgcn.s.barrier()
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; CHECK-NEXT: ret void
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;
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call void @llvm.amdgcn.s.barrier()
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ret void
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}
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define void @neg_empty_1() {
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; CHECK-LABEL: define {{[^@]+}}@neg_empty_1() {
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; CHECK-NEXT: call void @unknown()
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; CHECK-NEXT: ret void
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;
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call void @unknown()
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ret void
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}
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define void @neg_empty_2() {
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; CHECK-LABEL: define {{[^@]+}}@neg_empty_2() {
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; CHECK-NEXT: call void @aligned_barrier()
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; CHECK-NEXT: ret void
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;
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call void @aligned_barrier()
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ret void
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}
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@GC1 = constant i32 42
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@GC2 = addrspace(4) global i32 0
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@GPtr4 = addrspace(4) global i32 addrspace(4)* null
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define void @pos_constant_loads() {
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; CHECK-LABEL: define {{[^@]+}}@pos_constant_loads() {
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; CHECK-NEXT: [[ARG:%.*]] = load i32 addrspace(4)*, i32 addrspace(4)** addrspacecast (i32 addrspace(4)* addrspace(4)* @GPtr4 to i32 addrspace(4)**), align 8
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; CHECK-NEXT: [[A:%.*]] = load i32, i32* @GC1, align 4
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; CHECK-NEXT: [[B:%.*]] = load i32, i32* addrspacecast (i32 addrspace(4)* @GC2 to i32*), align 4
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; CHECK-NEXT: [[ARGC:%.*]] = addrspacecast i32 addrspace(4)* [[ARG]] to i32*
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; CHECK-NEXT: [[C:%.*]] = load i32, i32* [[ARGC]], align 4
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; CHECK-NEXT: call void @aligned_barrier()
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; CHECK-NEXT: [[D:%.*]] = add i32 [[A]], [[B]]
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; CHECK-NEXT: [[E:%.*]] = add i32 [[D]], [[C]]
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; CHECK-NEXT: call void @useI32(i32 [[E]])
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; CHECK-NEXT: ret void
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;
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%GPtr4c = addrspacecast i32 addrspace(4)*addrspace(4)* @GPtr4 to i32 addrspace(4)**
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%arg = load i32 addrspace(4)*, i32 addrspace(4)** %GPtr4c
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%a = load i32, i32* @GC1
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call void @aligned_barrier()
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%GC2c = addrspacecast i32 addrspace(4)* @GC2 to i32*
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%b = load i32, i32* %GC2c
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call void @aligned_barrier()
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%argc = addrspacecast i32 addrspace(4)* %arg to i32*
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%c = load i32, i32* %argc
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call void @aligned_barrier()
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%d = add i32 %a, %b
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%e = add i32 %d, %c
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call void @useI32(i32 %e)
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ret void
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}
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@G = global i32 42
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@GS = addrspace(3) global i32 0
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@GPtr = global i32* null
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; TODO: We could remove some of the barriers due to the lack of write effects.
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define void @neg_loads() {
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; CHECK-LABEL: define {{[^@]+}}@neg_loads() {
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; CHECK-NEXT: [[ARG:%.*]] = load i32*, i32** @GPtr, align 8
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; CHECK-NEXT: [[A:%.*]] = load i32, i32* @G, align 4
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; CHECK-NEXT: call void @aligned_barrier()
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; CHECK-NEXT: [[B:%.*]] = load i32, i32* addrspacecast (i32 addrspace(3)* @GS to i32*), align 4
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; CHECK-NEXT: call void @aligned_barrier()
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; CHECK-NEXT: [[C:%.*]] = load i32, i32* [[ARG]], align 4
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; CHECK-NEXT: call void @aligned_barrier()
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; CHECK-NEXT: [[D:%.*]] = add i32 [[A]], [[B]]
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; CHECK-NEXT: [[E:%.*]] = add i32 [[D]], [[C]]
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; CHECK-NEXT: call void @useI32(i32 [[E]])
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; CHECK-NEXT: ret void
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;
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%arg = load i32*, i32** @GPtr
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%a = load i32, i32* @G
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call void @aligned_barrier()
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%GSc = addrspacecast i32 addrspace(3)* @GS to i32*
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%b = load i32, i32* %GSc
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call void @aligned_barrier()
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%c = load i32, i32* %arg
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call void @aligned_barrier()
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%d = add i32 %a, %b
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%e = add i32 %d, %c
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call void @useI32(i32 %e)
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ret void
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}
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@PG1 = thread_local global i32 42
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@PG2 = addrspace(5) global i32 0
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@GPtr5 = global i32 addrspace(5)* null
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define void @pos_priv_mem() {
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; CHECK-LABEL: define {{[^@]+}}@pos_priv_mem() {
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; CHECK-NEXT: [[ARG:%.*]] = load i32 addrspace(5)*, i32 addrspace(5)** @GPtr5, align 8
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; CHECK-NEXT: [[LOC:%.*]] = alloca i32, align 4
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; CHECK-NEXT: [[A:%.*]] = load i32, i32* @PG1, align 4
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; CHECK-NEXT: store i32 [[A]], i32* [[LOC]], align 4
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; CHECK-NEXT: [[B:%.*]] = load i32, i32* addrspacecast (i32 addrspace(5)* @PG2 to i32*), align 4
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; CHECK-NEXT: call void @aligned_barrier()
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; CHECK-NEXT: [[ARGC:%.*]] = addrspacecast i32 addrspace(5)* [[ARG]] to i32*
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; CHECK-NEXT: store i32 [[B]], i32* [[ARGC]], align 4
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; CHECK-NEXT: store i32 [[A]], i32* @PG1, align 4
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; CHECK-NEXT: ret void
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;
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%arg = load i32 addrspace(5)*, i32 addrspace(5)** @GPtr5
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%loc = alloca i32
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%a = load i32, i32* @PG1
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call void @aligned_barrier()
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store i32 %a, i32* %loc
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%PG2c = addrspacecast i32 addrspace(5)* @PG2 to i32*
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%b = load i32, i32* %PG2c
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call void @aligned_barrier()
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%argc = addrspacecast i32 addrspace(5)* %arg to i32*
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store i32 %b, i32* %argc
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call void @aligned_barrier()
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%v = load i32, i32* %loc
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store i32 %v, i32* @PG1
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call void @aligned_barrier()
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ret void
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}
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@G1 = global i32 42
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@G2 = addrspace(1) global i32 0
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define void @neg_mem() {
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; CHECK-LABEL: define {{[^@]+}}@neg_mem() {
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; CHECK-NEXT: [[ARG:%.*]] = load i32*, i32** @GPtr, align 8
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; CHECK-NEXT: [[A:%.*]] = load i32, i32* @G1, align 4
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; CHECK-NEXT: call void @aligned_barrier()
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; CHECK-NEXT: store i32 [[A]], i32* [[ARG]], align 4
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; CHECK-NEXT: call void @aligned_barrier()
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; CHECK-NEXT: [[B:%.*]] = load i32, i32* addrspacecast (i32 addrspace(1)* @G2 to i32*), align 4
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; CHECK-NEXT: store i32 [[B]], i32* @G1, align 4
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; CHECK-NEXT: ret void
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;
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%arg = load i32*, i32** @GPtr
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%a = load i32, i32* @G1
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call void @aligned_barrier()
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store i32 %a, i32* %arg
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call void @aligned_barrier()
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%G2c = addrspacecast i32 addrspace(1)* @G2 to i32*
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%b = load i32, i32* %G2c
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store i32 %b, i32* @G1
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call void @aligned_barrier()
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ret void
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}
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define void @pos_multiple() {
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; CHECK-LABEL: define {{[^@]+}}@pos_multiple() {
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; CHECK-NEXT: call void @llvm.amdgcn.s.barrier()
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; CHECK-NEXT: ret void
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;
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call void @llvm.nvvm.barrier0()
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call void @aligned_barrier()
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call void @aligned_barrier()
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call void @llvm.amdgcn.s.barrier()
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call void @aligned_barrier()
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call void @llvm.nvvm.barrier0()
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call void @aligned_barrier()
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call void @aligned_barrier()
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ret void
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}
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!llvm.module.flags = !{!12,!13}
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!nvvm.annotations = !{!0,!1,!2,!3,!4,!5,!6,!7,!8,!9,!10,!11}
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!0 = !{void ()* @pos_empty_1, !"kernel", i32 1}
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!1 = !{void ()* @pos_empty_2, !"kernel", i32 1}
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!2 = !{void ()* @pos_empty_3, !"kernel", i32 1}
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!3 = !{void ()* @pos_empty_4, !"kernel", i32 1}
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!4 = !{void ()* @pos_empty_5, !"kernel", i32 1}
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!5 = !{void ()* @pos_empty_6, !"kernel", i32 1}
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!6 = !{void ()* @neg_empty_7, !"kernel", i32 1}
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!7 = !{void ()* @pos_constant_loads, !"kernel", i32 1}
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!8 = !{void ()* @neg_loads, !"kernel", i32 1}
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!9 = !{void ()* @pos_priv_mem, !"kernel", i32 1}
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!10 = !{void ()* @neg_mem, !"kernel", i32 1}
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!11 = !{void ()* @pos_multiple, !"kernel", i32 1}
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!12 = !{i32 7, !"openmp", i32 50}
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!13 = !{i32 7, !"openmp-device", i32 50}
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;.
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; CHECK: attributes #[[ATTR0:[0-9]+]] = { "llvm.assume"="ompx_aligned_barrier" }
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; CHECK: attributes #[[ATTR1:[0-9]+]] = { convergent nounwind }
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; CHECK: attributes #[[ATTR2:[0-9]+]] = { convergent nounwind willreturn }
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;.
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; CHECK: [[META0:![0-9]+]] = !{i32 7, !"openmp", i32 50}
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; CHECK: [[META1:![0-9]+]] = !{i32 7, !"openmp-device", i32 50}
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; CHECK: [[META2:![0-9]+]] = !{void ()* @pos_empty_1, !"kernel", i32 1}
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; CHECK: [[META3:![0-9]+]] = !{void ()* @pos_empty_2, !"kernel", i32 1}
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; CHECK: [[META4:![0-9]+]] = !{void ()* @pos_empty_3, !"kernel", i32 1}
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; CHECK: [[META5:![0-9]+]] = !{void ()* @pos_empty_4, !"kernel", i32 1}
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; CHECK: [[META6:![0-9]+]] = !{void ()* @pos_empty_5, !"kernel", i32 1}
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; CHECK: [[META7:![0-9]+]] = !{void ()* @pos_empty_6, !"kernel", i32 1}
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; CHECK: [[META8:![0-9]+]] = !{void ()* @neg_empty_7, !"kernel", i32 1}
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; CHECK: [[META9:![0-9]+]] = !{void ()* @pos_constant_loads, !"kernel", i32 1}
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; CHECK: [[META10:![0-9]+]] = !{void ()* @neg_loads, !"kernel", i32 1}
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; CHECK: [[META11:![0-9]+]] = !{void ()* @pos_priv_mem, !"kernel", i32 1}
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; CHECK: [[META12:![0-9]+]] = !{void ()* @neg_mem, !"kernel", i32 1}
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; CHECK: [[META13:![0-9]+]] = !{void ()* @pos_multiple, !"kernel", i32 1}
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;.
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