ee4ba9f3a1
Unfortunately, it seems we really do need to take the long route; start from the "merge" block, find (all the) "dispatch" blocks, and deal with each "dispatch" block separately, instead of simply starting from each "dispatch" block like it would logically make sense, otherwise we run into a number of other missing folds around `switch` formation, missing sinking/hoisting and phase ordering. This reverts commit 85628ce75b3084dc0f185a320152baf85b59aba7. This reverts commit c5fff9095342a792bf4b9a077fe3c3a83c4e566c. This reverts commit 34a98e1046e3aa55e5f26ab20a15e96b4034d25a. This reverts commit 1e353f092288309d74d380367aa50bbd383780ed.
120 lines
3.7 KiB
LLVM
120 lines
3.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt -passes='default<O3>' -enable-merge-functions -S < %s | FileCheck %s
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; TODO: These two functions should get merged, but currently aren't, because
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; the function merging pass is scheduled too early.
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target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
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target triple = "x86_64-unknown-linux-gnu"
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define i1 @test1(i32 %c) {
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; CHECK-LABEL: @test1(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[SWITCH_TABLEIDX:%.*]] = add i32 [[C:%.*]], -100
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; CHECK-NEXT: [[TMP0:%.*]] = icmp ult i32 [[SWITCH_TABLEIDX]], 20
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; CHECK-NEXT: [[SWITCH_CAST:%.*]] = trunc i32 [[SWITCH_TABLEIDX]] to i20
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; CHECK-NEXT: [[SWITCH_DOWNSHIFT:%.*]] = lshr i20 -490991, [[SWITCH_CAST]]
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; CHECK-NEXT: [[TMP1:%.*]] = and i20 [[SWITCH_DOWNSHIFT]], 1
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; CHECK-NEXT: [[SWITCH_MASKED:%.*]] = icmp ne i20 [[TMP1]], 0
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; CHECK-NEXT: [[I_0:%.*]] = select i1 [[TMP0]], i1 [[SWITCH_MASKED]], i1 false
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; CHECK-NEXT: ret i1 [[I_0]]
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;
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entry:
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%_4 = alloca i8, align 1
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%_3 = alloca i8, align 1
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%_2 = alloca i8, align 1
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%i = alloca i8, align 1
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%i1 = icmp eq i32 %c, 115
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br i1 %i1, label %bb10, label %bb11
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bb10: ; preds = %entry
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store i8 1, i8* %_4, align 1
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br label %bb12
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bb11: ; preds = %entry
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%_6 = icmp eq i32 %c, 109
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%i2 = zext i1 %_6 to i8
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store i8 %i2, i8* %_4, align 1
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br label %bb12
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bb12: ; preds = %bb11, %bb10
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%i3 = load i8, i8* %_4, align 1
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%i4 = trunc i8 %i3 to i1
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br i1 %i4, label %bb7, label %bb8
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bb8: ; preds = %bb12
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%_8 = icmp eq i32 %c, 104
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%i5 = zext i1 %_8 to i8
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store i8 %i5, i8* %_3, align 1
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br label %bb9
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bb7: ; preds = %bb12
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store i8 1, i8* %_3, align 1
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br label %bb9
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bb9: ; preds = %bb7, %bb8
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%i6 = load i8, i8* %_3, align 1
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%i7 = trunc i8 %i6 to i1
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br i1 %i7, label %bb4, label %bb5
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bb5: ; preds = %bb9
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%_10 = icmp eq i32 %c, 100
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%i8 = zext i1 %_10 to i8
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store i8 %i8, i8* %_2, align 1
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br label %bb6
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bb4: ; preds = %bb9
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store i8 1, i8* %_2, align 1
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br label %bb6
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bb6: ; preds = %bb4, %bb5
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%i9 = load i8, i8* %_2, align 1
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%i10 = trunc i8 %i9 to i1
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br i1 %i10, label %bb1, label %bb2
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bb2: ; preds = %bb6
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%_12 = icmp eq i32 %c, 119
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%i11 = zext i1 %_12 to i8
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store i8 %i11, i8* %i, align 1
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br label %bb3
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bb1: ; preds = %bb6
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store i8 1, i8* %i, align 1
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br label %bb3
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bb3: ; preds = %bb1, %bb2
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%i12 = load i8, i8* %i, align 1
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%i13 = trunc i8 %i12 to i1
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ret i1 %i13
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}
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define i1 @test2(i32 %c) {
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; CHECK-LABEL: @test2(
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; CHECK-NEXT: [[TMP2:%.*]] = tail call i1 @test1(i32 [[TMP0:%.*]]) #[[ATTR0:[0-9]+]]
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; CHECK-NEXT: ret i1 [[TMP2]]
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;
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entry:
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%i = alloca i8, align 1
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switch i32 %c, label %bb1 [
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i32 115, label %bb2
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i32 109, label %bb2
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i32 104, label %bb2
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i32 100, label %bb2
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i32 119, label %bb2
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]
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bb1: ; preds = %entry
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store i8 0, i8* %i, align 1
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br label %bb3
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bb2: ; preds = %entry, %entry, %entry, %entry, %entry
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store i8 1, i8* %i, align 1
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br label %bb3
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bb3: ; preds = %bb2, %bb1
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%i1 = load i8, i8* %i, align 1
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%i2 = trunc i8 %i1 to i1
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ret i1 %i2
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}
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