Simon Pilgrim 0c9c92ffc0 [X86][XOP] Tidyup VPHADD/VPHSUB unary horizontal ops default schedule class ...

Based off Agner and AMD SoG tables, the XOP VPHADD/VPHSUB unary horizontal ops are as fast as basic arithmetic ops, not the slower SSSE3 binary horizontal add/sub ops. This also matches what the bdver2 model already lists.

Noticed while investigating reduction add optimizations.

2022-03-03 12:07:48 +00:00

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AArch64

Partially revert "[SchedModels][CortexA55] Add ASIMD integer instructions"

2022-02-28 10:58:52 +00:00

AMDGPU

[MCA] Switching from conservatively guessing which instructions are

2022-01-11 13:50:14 -08:00

ARM

[MCA][InstrBuilder] Check for the presence of flag VariadicOpsAreDefs.

2021-06-15 09:52:38 +01:00

JSON/X86

[llvm-mca][JSON] Store extra information about driver flags used for the simulation

2021-07-16 09:18:40 +02:00

SystemZ

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X86

[X86][XOP] Tidyup VPHADD/VPHSUB unary horizontal ops default schedule class

2022-03-03 12:07:48 +00:00

invalid_input_file_name.test

[test] Use host platform specific error message substitution in lit tests

2021-01-29 07:16:30 -05:00

lit.local.cfg

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