6f288bd772
Having a separate counting method runs the risk of a mismatch between the actual reduction method and the counting method. Instead, create an Oracle that always returns true for shouldKeep(), run the reduction, and count how many times shouldKeep() was called. The module should not be modified if shouldKeep() always returns true. Reviewed By: Meinersbur Differential Revision: https://reviews.llvm.org/D113537
126 lines
3.9 KiB
C++
126 lines
3.9 KiB
C++
//===- ReduceInstructionsMIR.cpp - Specialized Delta Pass -----------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements a function which calls the Generic Delta pass in order
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// to reduce uninteresting MachineInstr from the MachineFunction.
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//
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//===----------------------------------------------------------------------===//
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#include "ReduceInstructionsMIR.h"
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#include "llvm/CodeGen/MachineDominators.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/TargetInstrInfo.h"
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using namespace llvm;
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static Register getPrevDefOfRCInMBB(MachineBasicBlock &MBB,
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MachineBasicBlock::reverse_iterator &RI,
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const TargetRegisterClass *RC,
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SetVector<MachineInstr *> &ExcludeMIs) {
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auto MRI = &MBB.getParent()->getRegInfo();
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for (MachineBasicBlock::reverse_instr_iterator E = MBB.instr_rend(); RI != E;
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++RI) {
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auto &MI = *RI;
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// All Def operands explicit and implicit.
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for (auto &MO : MI.operands()) {
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if (!MO.isReg() || !MO.isDef())
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continue;
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auto Reg = MO.getReg();
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if (Register::isPhysicalRegister(Reg))
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continue;
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if (MRI->getRegClass(Reg) == RC && !ExcludeMIs.count(MO.getParent()))
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return Reg;
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}
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}
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return 0;
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}
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static void extractInstrFromModule(Oracle &O, MachineFunction &MF) {
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MachineDominatorTree MDT;
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MDT.runOnMachineFunction(MF);
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auto MRI = &MF.getRegInfo();
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SetVector<MachineInstr *> ToDelete;
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MachineInstr *TopMI = nullptr;
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// Mark MIs for deletion according to some criteria.
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for (auto &MBB : MF) {
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for (auto &MI : MBB) {
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if (MI.isTerminator())
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continue;
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if (MBB.isEntryBlock() && !TopMI) {
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TopMI = &MI;
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continue;
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}
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if (!O.shouldKeep())
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ToDelete.insert(&MI);
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}
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}
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// For each MI to be deleted update users of regs defined by that MI to use
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// some other dominating definition (that is not to be deleted).
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for (auto *MI : ToDelete) {
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for (auto &MO : MI->operands()) {
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if (!MO.isReg() || !MO.isDef())
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continue;
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auto Reg = MO.getReg();
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if (Register::isPhysicalRegister(Reg))
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continue;
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auto UI = MRI->use_begin(Reg);
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auto UE = MRI->use_end();
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auto RegRC = MRI->getRegClass(Reg);
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Register NewReg = 0;
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// If this is not a physical register and there are some uses.
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if (UI != UE) {
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MachineBasicBlock::reverse_iterator RI(*MI);
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MachineBasicBlock *BB = MI->getParent();
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++RI;
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while (NewReg == 0 && BB) {
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NewReg = getPrevDefOfRCInMBB(*BB, RI, RegRC, ToDelete);
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// Prepare for idom(BB).
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if (auto *IDM = MDT.getNode(BB)->getIDom()) {
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BB = IDM->getBlock();
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RI = BB->rbegin();
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} else {
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BB = nullptr;
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}
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}
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}
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// If no dominating definition was found then add an implicit one to the
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// first instruction in the entry block.
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if (!NewReg && TopMI) {
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NewReg = MRI->createVirtualRegister(RegRC);
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TopMI->addOperand(MachineOperand::CreateReg(
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NewReg, true /*IsDef*/, true /*IsImp*/, false /*IsKill*/));
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}
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// Update all uses.
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while (UI != UE) {
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auto &UMO = *UI++;
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UMO.setReg(NewReg);
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}
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}
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}
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// Finally delete the MIs.
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for (auto *MI : ToDelete)
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MI->eraseFromParent();
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}
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void llvm::reduceInstructionsMIRDeltaPass(TestRunner &Test) {
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outs() << "*** Reducing Instructions...\n";
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runDeltaPass(Test, extractInstrFromModule);
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}
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