bed89970c3
Similar to #132569 for RISC-V, replace the unofficial `@plt` and `@gotpcrel` relocation specifiers, currently only used by clang -fexperimental-relative-c++-abi-vtables, with %pltpcrel %gotpcrel. The syntax is not used in humand-written assembly code, and is not supported by GNU assembler. Also replace the recent `@funcinit` with `%funcinit(x)`.
536 lines
20 KiB
C++
536 lines
20 KiB
C++
//===-- AArch64ELFObjectWriter.cpp - AArch64 ELF Writer -------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file handles ELF-specific object emission, converting LLVM's internal
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// fixups into the appropriate relocations.
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//
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//===----------------------------------------------------------------------===//
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#include "MCTargetDesc/AArch64FixupKinds.h"
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#include "MCTargetDesc/AArch64MCAsmInfo.h"
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#include "MCTargetDesc/AArch64MCTargetDesc.h"
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#include "llvm/BinaryFormat/ELF.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCELFObjectWriter.h"
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#include "llvm/MC/MCFixup.h"
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#include "llvm/MC/MCObjectWriter.h"
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#include "llvm/MC/MCSymbolELF.h"
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#include "llvm/MC/MCValue.h"
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#include "llvm/Support/ErrorHandling.h"
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#include <cassert>
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#include <cstdint>
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using namespace llvm;
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namespace {
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class AArch64ELFObjectWriter : public MCELFObjectTargetWriter {
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public:
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AArch64ELFObjectWriter(uint8_t OSABI, bool IsILP32);
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~AArch64ELFObjectWriter() override = default;
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protected:
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unsigned getRelocType(const MCFixup &, const MCValue &,
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bool IsPCRel) const override;
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bool needsRelocateWithSymbol(const MCValue &, unsigned Type) const override;
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bool isNonILP32reloc(const MCFixup &Fixup, AArch64::Specifier RefKind) const;
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void sortRelocs(std::vector<ELFRelocationEntry> &Relocs) override;
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bool IsILP32;
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};
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} // end anonymous namespace
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AArch64ELFObjectWriter::AArch64ELFObjectWriter(uint8_t OSABI, bool IsILP32)
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: MCELFObjectTargetWriter(/*Is64Bit*/ !IsILP32, OSABI, ELF::EM_AARCH64,
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/*HasRelocationAddend*/ true),
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IsILP32(IsILP32) {}
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#define R_CLS(rtype) \
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IsILP32 ? ELF::R_AARCH64_P32_##rtype : ELF::R_AARCH64_##rtype
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// assumes IsILP32 is true
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bool AArch64ELFObjectWriter::isNonILP32reloc(const MCFixup &Fixup,
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AArch64::Specifier RefKind) const {
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if (Fixup.getKind() != AArch64::fixup_aarch64_movw)
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return false;
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switch (RefKind) {
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case AArch64::S_ABS_G3:
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case AArch64::S_ABS_G2:
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case AArch64::S_ABS_G2_S:
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case AArch64::S_ABS_G2_NC:
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case AArch64::S_ABS_G1_S:
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case AArch64::S_ABS_G1_NC:
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case AArch64::S_DTPREL_G2:
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case AArch64::S_DTPREL_G1_NC:
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case AArch64::S_TPREL_G2:
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case AArch64::S_TPREL_G1_NC:
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case AArch64::S_GOTTPREL_G1:
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case AArch64::S_GOTTPREL_G0_NC:
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reportError(Fixup.getLoc(),
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"absolute MOV relocation is not supported in ILP32");
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return true;
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default:
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return false;
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}
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return false;
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}
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unsigned AArch64ELFObjectWriter::getRelocType(const MCFixup &Fixup,
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const MCValue &Target,
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bool IsPCRel) const {
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auto Kind = Fixup.getKind();
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AArch64::Specifier RefKind =
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static_cast<AArch64::Specifier>(Target.getSpecifier());
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AArch64::Specifier SymLoc = AArch64::getSymbolLoc(RefKind);
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bool IsNC = AArch64::isNotChecked(RefKind);
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switch (SymLoc) {
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case AArch64::S_DTPREL:
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case AArch64::S_GOTTPREL:
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case AArch64::S_TPREL:
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case AArch64::S_TLSDESC:
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case AArch64::S_TLSDESC_AUTH:
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if (auto *SA = const_cast<MCSymbol *>(Target.getAddSym()))
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static_cast<MCSymbolELF *>(SA)->setType(ELF::STT_TLS);
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break;
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default:
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break;
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}
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switch (RefKind) {
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case AArch64::S_GOTPCREL:
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case AArch64::S_PLT:
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if (Kind == FK_Data_4)
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break;
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// Only R_AARCH64_PLT32/R_AARCH64_GOTPCREL32 defined at present, but can
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// be extended to other sizes if additional relocations are defined.
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reportError(Fixup.getLoc(), AArch64::getSpecifierName(RefKind) +
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" can only be used in a .word directive");
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return ELF::R_AARCH64_NONE;
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default:
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break;
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}
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// Extract the relocation type from the fixup kind, after applying STT_TLS as
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// needed.
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if (mc::isRelocation(Fixup.getKind()))
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return Kind;
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if (IsPCRel) {
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switch (Kind) {
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case FK_Data_1:
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reportError(Fixup.getLoc(), "1-byte data relocations not supported");
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return ELF::R_AARCH64_NONE;
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case FK_Data_2:
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return R_CLS(PREL16);
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case FK_Data_4: {
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return R_CLS(PREL32);
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}
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case FK_Data_8:
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if (IsILP32) {
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reportError(Fixup.getLoc(), "8 byte PC relative data "
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"relocation is not supported in ILP32");
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return ELF::R_AARCH64_NONE;
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}
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return ELF::R_AARCH64_PREL64;
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case AArch64::fixup_aarch64_pcrel_adr_imm21:
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if (SymLoc == AArch64::S_GOT_AUTH) {
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if (IsILP32) {
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reportError(Fixup.getLoc(),
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"ADR AUTH relocation is not supported in ILP32");
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return ELF::R_AARCH64_NONE;
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}
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return ELF::R_AARCH64_AUTH_GOT_ADR_PREL_LO21;
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}
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if (SymLoc != AArch64::S_ABS)
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reportError(Fixup.getLoc(), "invalid symbol kind for ADR relocation");
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return R_CLS(ADR_PREL_LO21);
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case AArch64::fixup_aarch64_pcrel_adrp_imm21:
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if (SymLoc == AArch64::S_ABS && !IsNC)
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return R_CLS(ADR_PREL_PG_HI21);
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if (SymLoc == AArch64::S_ABS && IsNC) {
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if (IsILP32) {
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reportError(Fixup.getLoc(),
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"invalid fixup for 32-bit pcrel ADRP instruction "
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"VK_ABS VK_NC");
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return ELF::R_AARCH64_NONE;
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}
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return ELF::R_AARCH64_ADR_PREL_PG_HI21_NC;
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}
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if (SymLoc == AArch64::S_GOT && !IsNC)
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return R_CLS(ADR_GOT_PAGE);
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if (SymLoc == AArch64::S_GOT_AUTH && !IsNC) {
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if (IsILP32) {
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reportError(Fixup.getLoc(),
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"ADRP AUTH relocation is not supported in ILP32");
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return ELF::R_AARCH64_NONE;
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}
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return ELF::R_AARCH64_AUTH_ADR_GOT_PAGE;
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}
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if (SymLoc == AArch64::S_GOTTPREL && !IsNC)
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return R_CLS(TLSIE_ADR_GOTTPREL_PAGE21);
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if (SymLoc == AArch64::S_TLSDESC && !IsNC)
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return R_CLS(TLSDESC_ADR_PAGE21);
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if (SymLoc == AArch64::S_TLSDESC_AUTH && !IsNC) {
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if (IsILP32) {
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reportError(Fixup.getLoc(),
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"ADRP AUTH relocation is not supported in ILP32");
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return ELF::R_AARCH64_NONE;
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}
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return ELF::R_AARCH64_AUTH_TLSDESC_ADR_PAGE21;
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}
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reportError(Fixup.getLoc(), "invalid symbol kind for ADRP relocation");
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return ELF::R_AARCH64_NONE;
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case AArch64::fixup_aarch64_pcrel_branch26:
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return R_CLS(JUMP26);
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case AArch64::fixup_aarch64_pcrel_call26:
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return R_CLS(CALL26);
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case AArch64::fixup_aarch64_ldr_pcrel_imm19:
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if (SymLoc == AArch64::S_GOTTPREL)
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return R_CLS(TLSIE_LD_GOTTPREL_PREL19);
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if (SymLoc == AArch64::S_GOT)
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return R_CLS(GOT_LD_PREL19);
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if (SymLoc == AArch64::S_GOT_AUTH) {
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if (IsILP32) {
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reportError(Fixup.getLoc(),
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"LDR AUTH relocation is not supported in ILP32");
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return ELF::R_AARCH64_NONE;
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}
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return ELF::R_AARCH64_AUTH_GOT_LD_PREL19;
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}
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return R_CLS(LD_PREL_LO19);
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case AArch64::fixup_aarch64_pcrel_branch14:
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return R_CLS(TSTBR14);
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case AArch64::fixup_aarch64_pcrel_branch16:
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reportError(Fixup.getLoc(),
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"relocation of PAC/AUT instructions is not supported");
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return ELF::R_AARCH64_NONE;
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case AArch64::fixup_aarch64_pcrel_branch9:
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reportError(
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Fixup.getLoc(),
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"relocation of compare-and-branch instructions not supported");
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return ELF::R_AARCH64_NONE;
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case AArch64::fixup_aarch64_pcrel_branch19:
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return R_CLS(CONDBR19);
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default:
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reportError(Fixup.getLoc(), "Unsupported pc-relative fixup kind");
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return ELF::R_AARCH64_NONE;
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}
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} else {
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if (IsILP32 && isNonILP32reloc(Fixup, RefKind))
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return ELF::R_AARCH64_NONE;
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switch (Fixup.getKind()) {
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case FK_Data_1:
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reportError(Fixup.getLoc(), "1-byte data relocations not supported");
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return ELF::R_AARCH64_NONE;
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case FK_Data_2:
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return R_CLS(ABS16);
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case FK_Data_4:
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if (!IsILP32) {
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if (Target.getSpecifier() == AArch64::S_GOTPCREL)
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return ELF::R_AARCH64_GOTPCREL32;
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if (Target.getSpecifier() == AArch64::S_PLT)
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return ELF::R_AARCH64_PLT32;
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}
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return R_CLS(ABS32);
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case FK_Data_8: {
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if (IsILP32) {
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reportError(
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Fixup.getLoc(),
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"8 byte absolute data relocation is not supported in ILP32");
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return ELF::R_AARCH64_NONE;
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}
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if (RefKind == AArch64::S_AUTH || RefKind == AArch64::S_AUTHADDR)
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return ELF::R_AARCH64_AUTH_ABS64;
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if (RefKind == AArch64::S_FUNCINIT)
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return ELF::R_AARCH64_FUNCINIT64;
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return ELF::R_AARCH64_ABS64;
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}
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case AArch64::fixup_aarch64_add_imm12:
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if (RefKind == AArch64::S_DTPREL_HI12)
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return R_CLS(TLSLD_ADD_DTPREL_HI12);
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if (RefKind == AArch64::S_TPREL_HI12)
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return R_CLS(TLSLE_ADD_TPREL_HI12);
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if (RefKind == AArch64::S_DTPREL_LO12_NC)
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return R_CLS(TLSLD_ADD_DTPREL_LO12_NC);
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if (RefKind == AArch64::S_DTPREL_LO12)
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return R_CLS(TLSLD_ADD_DTPREL_LO12);
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if (RefKind == AArch64::S_TPREL_LO12_NC)
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return R_CLS(TLSLE_ADD_TPREL_LO12_NC);
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if (RefKind == AArch64::S_TPREL_LO12)
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return R_CLS(TLSLE_ADD_TPREL_LO12);
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if (RefKind == AArch64::S_TLSDESC_LO12)
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return R_CLS(TLSDESC_ADD_LO12);
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if (RefKind == AArch64::S_TLSDESC_AUTH_LO12) {
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if (IsILP32) {
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reportError(Fixup.getLoc(),
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"ADD AUTH relocation is not supported in ILP32");
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return ELF::R_AARCH64_NONE;
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}
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return ELF::R_AARCH64_AUTH_TLSDESC_ADD_LO12;
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}
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if (RefKind == AArch64::S_GOT_AUTH_LO12 && IsNC) {
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if (IsILP32) {
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reportError(Fixup.getLoc(),
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"ADD AUTH relocation is not supported in ILP32");
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return ELF::R_AARCH64_NONE;
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}
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return ELF::R_AARCH64_AUTH_GOT_ADD_LO12_NC;
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}
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if (SymLoc == AArch64::S_ABS && IsNC)
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return R_CLS(ADD_ABS_LO12_NC);
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reportError(Fixup.getLoc(), "invalid fixup for add (uimm12) instruction");
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return ELF::R_AARCH64_NONE;
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case AArch64::fixup_aarch64_ldst_imm12_scale1:
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if (SymLoc == AArch64::S_ABS && IsNC)
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return R_CLS(LDST8_ABS_LO12_NC);
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if (SymLoc == AArch64::S_DTPREL && !IsNC)
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return R_CLS(TLSLD_LDST8_DTPREL_LO12);
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if (SymLoc == AArch64::S_DTPREL && IsNC)
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return R_CLS(TLSLD_LDST8_DTPREL_LO12_NC);
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if (SymLoc == AArch64::S_TPREL && !IsNC)
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return R_CLS(TLSLE_LDST8_TPREL_LO12);
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if (SymLoc == AArch64::S_TPREL && IsNC)
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return R_CLS(TLSLE_LDST8_TPREL_LO12_NC);
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reportError(Fixup.getLoc(),
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"invalid fixup for 8-bit load/store instruction");
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return ELF::R_AARCH64_NONE;
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case AArch64::fixup_aarch64_ldst_imm12_scale2:
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if (SymLoc == AArch64::S_ABS && IsNC)
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return R_CLS(LDST16_ABS_LO12_NC);
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if (SymLoc == AArch64::S_DTPREL && !IsNC)
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return R_CLS(TLSLD_LDST16_DTPREL_LO12);
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if (SymLoc == AArch64::S_DTPREL && IsNC)
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return R_CLS(TLSLD_LDST16_DTPREL_LO12_NC);
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if (SymLoc == AArch64::S_TPREL && !IsNC)
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return R_CLS(TLSLE_LDST16_TPREL_LO12);
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if (SymLoc == AArch64::S_TPREL && IsNC)
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return R_CLS(TLSLE_LDST16_TPREL_LO12_NC);
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reportError(Fixup.getLoc(),
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"invalid fixup for 16-bit load/store instruction");
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return ELF::R_AARCH64_NONE;
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case AArch64::fixup_aarch64_ldst_imm12_scale4:
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if (SymLoc == AArch64::S_ABS && IsNC)
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return R_CLS(LDST32_ABS_LO12_NC);
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if (SymLoc == AArch64::S_DTPREL && !IsNC)
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return R_CLS(TLSLD_LDST32_DTPREL_LO12);
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if (SymLoc == AArch64::S_DTPREL && IsNC)
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return R_CLS(TLSLD_LDST32_DTPREL_LO12_NC);
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if (SymLoc == AArch64::S_TPREL && !IsNC)
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return R_CLS(TLSLE_LDST32_TPREL_LO12);
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if (SymLoc == AArch64::S_TPREL && IsNC)
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return R_CLS(TLSLE_LDST32_TPREL_LO12_NC);
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if (SymLoc == AArch64::S_GOT && IsNC) {
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if (IsILP32)
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return ELF::R_AARCH64_P32_LD32_GOT_LO12_NC;
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reportError(Fixup.getLoc(), "4 byte unchecked GOT load/store "
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"relocation is not supported in LP64");
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return ELF::R_AARCH64_NONE;
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}
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if (SymLoc == AArch64::S_GOT && !IsNC) {
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if (IsILP32) {
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reportError(
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Fixup.getLoc(),
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"4 byte checked GOT load/store relocation is not supported");
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}
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return ELF::R_AARCH64_NONE;
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}
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if (SymLoc == AArch64::S_GOTTPREL && IsNC) {
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if (IsILP32)
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return ELF::R_AARCH64_P32_TLSIE_LD32_GOTTPREL_LO12_NC;
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reportError(Fixup.getLoc(), "32-bit load/store "
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"relocation is not supported in LP64");
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return ELF::R_AARCH64_NONE;
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}
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if (SymLoc == AArch64::S_TLSDESC && !IsNC) {
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if (IsILP32)
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return ELF::R_AARCH64_P32_TLSDESC_LD32_LO12;
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reportError(
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Fixup.getLoc(),
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"4 byte TLSDESC load/store relocation is not supported in LP64");
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return ELF::R_AARCH64_NONE;
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}
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reportError(Fixup.getLoc(),
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"invalid fixup for 32-bit load/store instruction "
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"fixup_aarch64_ldst_imm12_scale4");
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return ELF::R_AARCH64_NONE;
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case AArch64::fixup_aarch64_ldst_imm12_scale8:
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if (SymLoc == AArch64::S_ABS && IsNC)
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return R_CLS(LDST64_ABS_LO12_NC);
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if ((SymLoc == AArch64::S_GOT || SymLoc == AArch64::S_GOT_AUTH) && IsNC) {
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AArch64::Specifier AddressLoc = AArch64::getAddressFrag(RefKind);
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bool IsAuth = (SymLoc == AArch64::S_GOT_AUTH);
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if (!IsILP32) {
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if (AddressLoc == AArch64::S_LO15)
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return ELF::R_AARCH64_LD64_GOTPAGE_LO15;
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return (IsAuth ? ELF::R_AARCH64_AUTH_LD64_GOT_LO12_NC
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: ELF::R_AARCH64_LD64_GOT_LO12_NC);
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}
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reportError(Fixup.getLoc(),
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"64-bit load/store relocation is not supported in ILP32");
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return ELF::R_AARCH64_NONE;
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}
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if (SymLoc == AArch64::S_DTPREL && !IsNC)
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return R_CLS(TLSLD_LDST64_DTPREL_LO12);
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if (SymLoc == AArch64::S_DTPREL && IsNC)
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return R_CLS(TLSLD_LDST64_DTPREL_LO12_NC);
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if (SymLoc == AArch64::S_TPREL && !IsNC)
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return R_CLS(TLSLE_LDST64_TPREL_LO12);
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if (SymLoc == AArch64::S_TPREL && IsNC)
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return R_CLS(TLSLE_LDST64_TPREL_LO12_NC);
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if (SymLoc == AArch64::S_GOTTPREL && IsNC) {
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if (!IsILP32)
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return ELF::R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC;
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reportError(Fixup.getLoc(),
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"64-bit load/store relocation is not supported in ILP32");
|
|
return ELF::R_AARCH64_NONE;
|
|
}
|
|
if (SymLoc == AArch64::S_TLSDESC) {
|
|
if (!IsILP32)
|
|
return ELF::R_AARCH64_TLSDESC_LD64_LO12;
|
|
reportError(Fixup.getLoc(),
|
|
"64-bit load/store relocation is not supported in ILP32");
|
|
return ELF::R_AARCH64_NONE;
|
|
}
|
|
if (SymLoc == AArch64::S_TLSDESC_AUTH) {
|
|
if (!IsILP32)
|
|
return ELF::R_AARCH64_AUTH_TLSDESC_LD64_LO12;
|
|
reportError(
|
|
Fixup.getLoc(),
|
|
"64-bit load/store AUTH relocation is not supported in ILP32");
|
|
return ELF::R_AARCH64_NONE;
|
|
}
|
|
reportError(Fixup.getLoc(),
|
|
"invalid fixup for 64-bit load/store instruction");
|
|
return ELF::R_AARCH64_NONE;
|
|
case AArch64::fixup_aarch64_ldst_imm12_scale16:
|
|
if (SymLoc == AArch64::S_ABS && IsNC)
|
|
return R_CLS(LDST128_ABS_LO12_NC);
|
|
if (SymLoc == AArch64::S_DTPREL && !IsNC)
|
|
return R_CLS(TLSLD_LDST128_DTPREL_LO12);
|
|
if (SymLoc == AArch64::S_DTPREL && IsNC)
|
|
return R_CLS(TLSLD_LDST128_DTPREL_LO12_NC);
|
|
if (SymLoc == AArch64::S_TPREL && !IsNC)
|
|
return R_CLS(TLSLE_LDST128_TPREL_LO12);
|
|
if (SymLoc == AArch64::S_TPREL && IsNC)
|
|
return R_CLS(TLSLE_LDST128_TPREL_LO12_NC);
|
|
|
|
reportError(Fixup.getLoc(),
|
|
"invalid fixup for 128-bit load/store instruction");
|
|
return ELF::R_AARCH64_NONE;
|
|
// ILP32 case not reached here, tested with isNonILP32reloc
|
|
case AArch64::fixup_aarch64_movw:
|
|
if (RefKind == AArch64::S_ABS_G3)
|
|
return ELF::R_AARCH64_MOVW_UABS_G3;
|
|
if (RefKind == AArch64::S_ABS_G2)
|
|
return ELF::R_AARCH64_MOVW_UABS_G2;
|
|
if (RefKind == AArch64::S_ABS_G2_S)
|
|
return ELF::R_AARCH64_MOVW_SABS_G2;
|
|
if (RefKind == AArch64::S_ABS_G2_NC)
|
|
return ELF::R_AARCH64_MOVW_UABS_G2_NC;
|
|
if (RefKind == AArch64::S_ABS_G1)
|
|
return R_CLS(MOVW_UABS_G1);
|
|
if (RefKind == AArch64::S_ABS_G1_S)
|
|
return ELF::R_AARCH64_MOVW_SABS_G1;
|
|
if (RefKind == AArch64::S_ABS_G1_NC)
|
|
return ELF::R_AARCH64_MOVW_UABS_G1_NC;
|
|
if (RefKind == AArch64::S_ABS_G0)
|
|
return R_CLS(MOVW_UABS_G0);
|
|
if (RefKind == AArch64::S_ABS_G0_S)
|
|
return R_CLS(MOVW_SABS_G0);
|
|
if (RefKind == AArch64::S_ABS_G0_NC)
|
|
return R_CLS(MOVW_UABS_G0_NC);
|
|
if (RefKind == AArch64::S_PREL_G3)
|
|
return ELF::R_AARCH64_MOVW_PREL_G3;
|
|
if (RefKind == AArch64::S_PREL_G2)
|
|
return ELF::R_AARCH64_MOVW_PREL_G2;
|
|
if (RefKind == AArch64::S_PREL_G2_NC)
|
|
return ELF::R_AARCH64_MOVW_PREL_G2_NC;
|
|
if (RefKind == AArch64::S_PREL_G1)
|
|
return R_CLS(MOVW_PREL_G1);
|
|
if (RefKind == AArch64::S_PREL_G1_NC)
|
|
return ELF::R_AARCH64_MOVW_PREL_G1_NC;
|
|
if (RefKind == AArch64::S_PREL_G0)
|
|
return R_CLS(MOVW_PREL_G0);
|
|
if (RefKind == AArch64::S_PREL_G0_NC)
|
|
return R_CLS(MOVW_PREL_G0_NC);
|
|
if (RefKind == AArch64::S_DTPREL_G2)
|
|
return ELF::R_AARCH64_TLSLD_MOVW_DTPREL_G2;
|
|
if (RefKind == AArch64::S_DTPREL_G1)
|
|
return R_CLS(TLSLD_MOVW_DTPREL_G1);
|
|
if (RefKind == AArch64::S_DTPREL_G1_NC)
|
|
return ELF::R_AARCH64_TLSLD_MOVW_DTPREL_G1_NC;
|
|
if (RefKind == AArch64::S_DTPREL_G0)
|
|
return R_CLS(TLSLD_MOVW_DTPREL_G0);
|
|
if (RefKind == AArch64::S_DTPREL_G0_NC)
|
|
return R_CLS(TLSLD_MOVW_DTPREL_G0_NC);
|
|
if (RefKind == AArch64::S_TPREL_G2)
|
|
return ELF::R_AARCH64_TLSLE_MOVW_TPREL_G2;
|
|
if (RefKind == AArch64::S_TPREL_G1)
|
|
return R_CLS(TLSLE_MOVW_TPREL_G1);
|
|
if (RefKind == AArch64::S_TPREL_G1_NC)
|
|
return ELF::R_AARCH64_TLSLE_MOVW_TPREL_G1_NC;
|
|
if (RefKind == AArch64::S_TPREL_G0)
|
|
return R_CLS(TLSLE_MOVW_TPREL_G0);
|
|
if (RefKind == AArch64::S_TPREL_G0_NC)
|
|
return R_CLS(TLSLE_MOVW_TPREL_G0_NC);
|
|
if (RefKind == AArch64::S_GOTTPREL_G1)
|
|
return ELF::R_AARCH64_TLSIE_MOVW_GOTTPREL_G1;
|
|
if (RefKind == AArch64::S_GOTTPREL_G0_NC)
|
|
return ELF::R_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC;
|
|
reportError(Fixup.getLoc(), "invalid fixup for movz/movk instruction");
|
|
return ELF::R_AARCH64_NONE;
|
|
default:
|
|
reportError(Fixup.getLoc(), "Unknown ELF relocation type");
|
|
return ELF::R_AARCH64_NONE;
|
|
}
|
|
}
|
|
|
|
llvm_unreachable("Unimplemented fixup -> relocation");
|
|
}
|
|
|
|
bool AArch64ELFObjectWriter::needsRelocateWithSymbol(const MCValue &Val,
|
|
unsigned) const {
|
|
// For memory-tagged symbols, ensure that the relocation uses the symbol. For
|
|
// tagged symbols, we emit an empty relocation (R_AARCH64_NONE) in a special
|
|
// section (SHT_AARCH64_MEMTAG_GLOBALS_STATIC) to indicate to the linker that
|
|
// this global needs to be tagged. In addition, the linker needs to know
|
|
// whether to emit a special addend when relocating `end` symbols, and this
|
|
// can only be determined by the attributes of the symbol itself.
|
|
if (Val.getAddSym() &&
|
|
static_cast<const MCSymbolELF *>(Val.getAddSym())->isMemtag())
|
|
return true;
|
|
|
|
if ((Val.getSpecifier() & AArch64::S_GOT) == AArch64::S_GOT)
|
|
return true;
|
|
return is_contained({AArch64::S_GOTPCREL, AArch64::S_PLT},
|
|
Val.getSpecifier());
|
|
}
|
|
|
|
void AArch64ELFObjectWriter::sortRelocs(
|
|
std::vector<ELFRelocationEntry> &Relocs) {
|
|
// PATCHINST relocations should be applied last because they may overwrite the
|
|
// whole instruction and so should take precedence over other relocations that
|
|
// modify operands of the original instruction.
|
|
std::stable_partition(Relocs.begin(), Relocs.end(),
|
|
[](const ELFRelocationEntry &R) {
|
|
return R.Type != ELF::R_AARCH64_PATCHINST;
|
|
});
|
|
}
|
|
|
|
std::unique_ptr<MCObjectTargetWriter>
|
|
llvm::createAArch64ELFObjectWriter(uint8_t OSABI, bool IsILP32) {
|
|
return std::make_unique<AArch64ELFObjectWriter>(OSABI, IsILP32);
|
|
}
|