453 lines
18 KiB
C++
453 lines
18 KiB
C++
//===-- SPIRVGlobalRegistry.cpp - SPIR-V Global Registry --------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the implementation of the SPIRVGlobalRegistry class,
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// which is used to maintain rich type information required for SPIR-V even
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// after lowering from LLVM IR to GMIR. It can convert an llvm::Type into
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// an OpTypeXXX instruction, and map it to a virtual register. Also it builds
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// and supports consistency of constants and global variables.
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//
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//===----------------------------------------------------------------------===//
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#include "SPIRVGlobalRegistry.h"
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#include "SPIRV.h"
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#include "SPIRVSubtarget.h"
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#include "SPIRVTargetMachine.h"
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#include "SPIRVUtils.h"
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using namespace llvm;
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SPIRVGlobalRegistry::SPIRVGlobalRegistry(unsigned PointerSize)
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: PointerSize(PointerSize) {}
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SPIRVType *SPIRVGlobalRegistry::assignTypeToVReg(
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const Type *Type, Register VReg, MachineIRBuilder &MIRBuilder,
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SPIRV::AccessQualifier AccessQual, bool EmitIR) {
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SPIRVType *SpirvType =
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getOrCreateSPIRVType(Type, MIRBuilder, AccessQual, EmitIR);
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assignSPIRVTypeToVReg(SpirvType, VReg, MIRBuilder);
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return SpirvType;
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}
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void SPIRVGlobalRegistry::assignSPIRVTypeToVReg(SPIRVType *SpirvType,
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Register VReg,
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MachineIRBuilder &MIRBuilder) {
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VRegToTypeMap[&MIRBuilder.getMF()][VReg] = SpirvType;
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}
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static Register createTypeVReg(MachineIRBuilder &MIRBuilder) {
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auto &MRI = MIRBuilder.getMF().getRegInfo();
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auto Res = MRI.createGenericVirtualRegister(LLT::scalar(32));
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MRI.setRegClass(Res, &SPIRV::TYPERegClass);
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return Res;
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}
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static Register createTypeVReg(MachineRegisterInfo &MRI) {
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auto Res = MRI.createGenericVirtualRegister(LLT::scalar(32));
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MRI.setRegClass(Res, &SPIRV::TYPERegClass);
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return Res;
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}
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SPIRVType *SPIRVGlobalRegistry::getOpTypeBool(MachineIRBuilder &MIRBuilder) {
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return MIRBuilder.buildInstr(SPIRV::OpTypeBool)
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.addDef(createTypeVReg(MIRBuilder));
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}
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SPIRVType *SPIRVGlobalRegistry::getOpTypeInt(uint32_t Width,
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MachineIRBuilder &MIRBuilder,
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bool IsSigned) {
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auto MIB = MIRBuilder.buildInstr(SPIRV::OpTypeInt)
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.addDef(createTypeVReg(MIRBuilder))
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.addImm(Width)
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.addImm(IsSigned ? 1 : 0);
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return MIB;
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}
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SPIRVType *SPIRVGlobalRegistry::getOpTypeFloat(uint32_t Width,
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MachineIRBuilder &MIRBuilder) {
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auto MIB = MIRBuilder.buildInstr(SPIRV::OpTypeFloat)
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.addDef(createTypeVReg(MIRBuilder))
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.addImm(Width);
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return MIB;
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}
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SPIRVType *SPIRVGlobalRegistry::getOpTypeVoid(MachineIRBuilder &MIRBuilder) {
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return MIRBuilder.buildInstr(SPIRV::OpTypeVoid)
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.addDef(createTypeVReg(MIRBuilder));
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}
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SPIRVType *SPIRVGlobalRegistry::getOpTypeVector(uint32_t NumElems,
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SPIRVType *ElemType,
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MachineIRBuilder &MIRBuilder) {
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auto EleOpc = ElemType->getOpcode();
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assert((EleOpc == SPIRV::OpTypeInt || EleOpc == SPIRV::OpTypeFloat ||
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EleOpc == SPIRV::OpTypeBool) &&
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"Invalid vector element type");
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auto MIB = MIRBuilder.buildInstr(SPIRV::OpTypeVector)
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.addDef(createTypeVReg(MIRBuilder))
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.addUse(getSPIRVTypeID(ElemType))
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.addImm(NumElems);
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return MIB;
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}
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Register SPIRVGlobalRegistry::buildConstantInt(uint64_t Val,
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MachineIRBuilder &MIRBuilder,
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SPIRVType *SpvType,
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bool EmitIR) {
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auto &MF = MIRBuilder.getMF();
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Register Res;
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const IntegerType *LLVMIntTy;
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if (SpvType)
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LLVMIntTy = cast<IntegerType>(getTypeForSPIRVType(SpvType));
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else
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LLVMIntTy = IntegerType::getInt32Ty(MF.getFunction().getContext());
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// Find a constant in DT or build a new one.
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const auto ConstInt =
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ConstantInt::get(const_cast<IntegerType *>(LLVMIntTy), Val);
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unsigned BitWidth = SpvType ? getScalarOrVectorBitWidth(SpvType) : 32;
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Res = MF.getRegInfo().createGenericVirtualRegister(LLT::scalar(BitWidth));
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assignTypeToVReg(LLVMIntTy, Res, MIRBuilder);
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if (EmitIR)
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MIRBuilder.buildConstant(Res, *ConstInt);
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else
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MIRBuilder.buildInstr(SPIRV::OpConstantI)
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.addDef(Res)
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.addImm(ConstInt->getSExtValue());
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return Res;
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}
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Register SPIRVGlobalRegistry::buildConstantFP(APFloat Val,
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MachineIRBuilder &MIRBuilder,
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SPIRVType *SpvType) {
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auto &MF = MIRBuilder.getMF();
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Register Res;
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const Type *LLVMFPTy;
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if (SpvType) {
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LLVMFPTy = getTypeForSPIRVType(SpvType);
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assert(LLVMFPTy->isFloatingPointTy());
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} else {
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LLVMFPTy = IntegerType::getFloatTy(MF.getFunction().getContext());
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}
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// Find a constant in DT or build a new one.
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const auto ConstFP = ConstantFP::get(LLVMFPTy->getContext(), Val);
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unsigned BitWidth = SpvType ? getScalarOrVectorBitWidth(SpvType) : 32;
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Res = MF.getRegInfo().createGenericVirtualRegister(LLT::scalar(BitWidth));
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assignTypeToVReg(LLVMFPTy, Res, MIRBuilder);
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MIRBuilder.buildFConstant(Res, *ConstFP);
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return Res;
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}
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Register SPIRVGlobalRegistry::buildGlobalVariable(
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Register ResVReg, SPIRVType *BaseType, StringRef Name,
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const GlobalValue *GV, SPIRV::StorageClass Storage,
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const MachineInstr *Init, bool IsConst, bool HasLinkageTy,
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SPIRV::LinkageType LinkageType, MachineIRBuilder &MIRBuilder,
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bool IsInstSelector) {
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const GlobalVariable *GVar = nullptr;
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if (GV)
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GVar = cast<const GlobalVariable>(GV);
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else {
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// If GV is not passed explicitly, use the name to find or construct
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// the global variable.
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Module *M = MIRBuilder.getMF().getFunction().getParent();
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GVar = M->getGlobalVariable(Name);
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if (GVar == nullptr) {
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const Type *Ty = getTypeForSPIRVType(BaseType); // TODO: check type.
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GVar = new GlobalVariable(*M, const_cast<Type *>(Ty), false,
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GlobalValue::ExternalLinkage, nullptr,
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Twine(Name));
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}
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GV = GVar;
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}
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Register Reg;
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auto MIB = MIRBuilder.buildInstr(SPIRV::OpVariable)
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.addDef(ResVReg)
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.addUse(getSPIRVTypeID(BaseType))
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.addImm(static_cast<uint32_t>(Storage));
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if (Init != 0) {
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MIB.addUse(Init->getOperand(0).getReg());
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}
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// ISel may introduce a new register on this step, so we need to add it to
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// DT and correct its type avoiding fails on the next stage.
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if (IsInstSelector) {
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const auto &Subtarget = CurMF->getSubtarget();
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constrainSelectedInstRegOperands(*MIB, *Subtarget.getInstrInfo(),
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*Subtarget.getRegisterInfo(),
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*Subtarget.getRegBankInfo());
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}
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Reg = MIB->getOperand(0).getReg();
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// Set to Reg the same type as ResVReg has.
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auto MRI = MIRBuilder.getMRI();
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assert(MRI->getType(ResVReg).isPointer() && "Pointer type is expected");
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if (Reg != ResVReg) {
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LLT RegLLTy = LLT::pointer(MRI->getType(ResVReg).getAddressSpace(), 32);
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MRI->setType(Reg, RegLLTy);
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assignSPIRVTypeToVReg(BaseType, Reg, MIRBuilder);
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}
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// If it's a global variable with name, output OpName for it.
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if (GVar && GVar->hasName())
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buildOpName(Reg, GVar->getName(), MIRBuilder);
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// Output decorations for the GV.
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// TODO: maybe move to GenerateDecorations pass.
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if (IsConst)
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buildOpDecorate(Reg, MIRBuilder, SPIRV::Decoration::Constant, {});
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if (GVar && GVar->getAlign().valueOrOne().value() != 1)
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buildOpDecorate(
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Reg, MIRBuilder, SPIRV::Decoration::Alignment,
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{static_cast<uint32_t>(GVar->getAlign().valueOrOne().value())});
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if (HasLinkageTy)
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buildOpDecorate(Reg, MIRBuilder, SPIRV::Decoration::LinkageAttributes,
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{static_cast<uint32_t>(LinkageType)}, Name);
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return Reg;
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}
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SPIRVType *SPIRVGlobalRegistry::getOpTypeArray(uint32_t NumElems,
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SPIRVType *ElemType,
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MachineIRBuilder &MIRBuilder,
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bool EmitIR) {
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assert((ElemType->getOpcode() != SPIRV::OpTypeVoid) &&
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"Invalid array element type");
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Register NumElementsVReg =
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buildConstantInt(NumElems, MIRBuilder, nullptr, EmitIR);
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auto MIB = MIRBuilder.buildInstr(SPIRV::OpTypeArray)
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.addDef(createTypeVReg(MIRBuilder))
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.addUse(getSPIRVTypeID(ElemType))
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.addUse(NumElementsVReg);
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return MIB;
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}
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SPIRVType *SPIRVGlobalRegistry::getOpTypePointer(SPIRV::StorageClass SC,
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SPIRVType *ElemType,
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MachineIRBuilder &MIRBuilder) {
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auto MIB = MIRBuilder.buildInstr(SPIRV::OpTypePointer)
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.addDef(createTypeVReg(MIRBuilder))
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.addImm(static_cast<uint32_t>(SC))
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.addUse(getSPIRVTypeID(ElemType));
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return MIB;
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}
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SPIRVType *SPIRVGlobalRegistry::getOpTypeFunction(
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SPIRVType *RetType, const SmallVectorImpl<SPIRVType *> &ArgTypes,
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MachineIRBuilder &MIRBuilder) {
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auto MIB = MIRBuilder.buildInstr(SPIRV::OpTypeFunction)
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.addDef(createTypeVReg(MIRBuilder))
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.addUse(getSPIRVTypeID(RetType));
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for (const SPIRVType *ArgType : ArgTypes)
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MIB.addUse(getSPIRVTypeID(ArgType));
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return MIB;
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}
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SPIRVType *SPIRVGlobalRegistry::createSPIRVType(const Type *Ty,
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MachineIRBuilder &MIRBuilder,
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SPIRV::AccessQualifier AccQual,
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bool EmitIR) {
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if (auto IType = dyn_cast<IntegerType>(Ty)) {
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const unsigned Width = IType->getBitWidth();
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return Width == 1 ? getOpTypeBool(MIRBuilder)
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: getOpTypeInt(Width, MIRBuilder, false);
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}
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if (Ty->isFloatingPointTy())
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return getOpTypeFloat(Ty->getPrimitiveSizeInBits(), MIRBuilder);
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if (Ty->isVoidTy())
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return getOpTypeVoid(MIRBuilder);
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if (Ty->isVectorTy()) {
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auto El = getOrCreateSPIRVType(cast<FixedVectorType>(Ty)->getElementType(),
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MIRBuilder);
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return getOpTypeVector(cast<FixedVectorType>(Ty)->getNumElements(), El,
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MIRBuilder);
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}
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if (Ty->isArrayTy()) {
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auto *El = getOrCreateSPIRVType(Ty->getArrayElementType(), MIRBuilder);
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return getOpTypeArray(Ty->getArrayNumElements(), El, MIRBuilder, EmitIR);
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}
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assert(!isa<StructType>(Ty) && "Unsupported StructType");
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if (auto FType = dyn_cast<FunctionType>(Ty)) {
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SPIRVType *RetTy = getOrCreateSPIRVType(FType->getReturnType(), MIRBuilder);
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SmallVector<SPIRVType *, 4> ParamTypes;
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for (const auto &t : FType->params()) {
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ParamTypes.push_back(getOrCreateSPIRVType(t, MIRBuilder));
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}
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return getOpTypeFunction(RetTy, ParamTypes, MIRBuilder);
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}
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if (auto PType = dyn_cast<PointerType>(Ty)) {
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Type *ElemType = PType->getPointerElementType();
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// Some OpenCL and SPIRV builtins like image2d_t are passed in as pointers,
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// but should be treated as custom types like OpTypeImage.
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assert(!isa<StructType>(ElemType) && "Unsupported StructType pointer");
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// Otherwise, treat it as a regular pointer type.
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auto SC = addressSpaceToStorageClass(PType->getAddressSpace());
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SPIRVType *SpvElementType = getOrCreateSPIRVType(
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ElemType, MIRBuilder, SPIRV::AccessQualifier::ReadWrite, EmitIR);
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return getOpTypePointer(SC, SpvElementType, MIRBuilder);
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}
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llvm_unreachable("Unable to convert LLVM type to SPIRVType");
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}
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SPIRVType *SPIRVGlobalRegistry::getSPIRVTypeForVReg(Register VReg) const {
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auto t = VRegToTypeMap.find(CurMF);
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if (t != VRegToTypeMap.end()) {
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auto tt = t->second.find(VReg);
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if (tt != t->second.end())
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return tt->second;
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}
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return nullptr;
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}
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SPIRVType *SPIRVGlobalRegistry::getOrCreateSPIRVType(
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const Type *Type, MachineIRBuilder &MIRBuilder,
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SPIRV::AccessQualifier AccessQual, bool EmitIR) {
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SPIRVType *SpirvType = createSPIRVType(Type, MIRBuilder, AccessQual, EmitIR);
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VRegToTypeMap[&MIRBuilder.getMF()][getSPIRVTypeID(SpirvType)] = SpirvType;
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SPIRVToLLVMType[SpirvType] = Type;
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return SpirvType;
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}
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bool SPIRVGlobalRegistry::isScalarOfType(Register VReg,
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unsigned TypeOpcode) const {
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SPIRVType *Type = getSPIRVTypeForVReg(VReg);
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assert(Type && "isScalarOfType VReg has no type assigned");
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return Type->getOpcode() == TypeOpcode;
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}
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bool SPIRVGlobalRegistry::isScalarOrVectorOfType(Register VReg,
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unsigned TypeOpcode) const {
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SPIRVType *Type = getSPIRVTypeForVReg(VReg);
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assert(Type && "isScalarOrVectorOfType VReg has no type assigned");
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if (Type->getOpcode() == TypeOpcode)
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return true;
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if (Type->getOpcode() == SPIRV::OpTypeVector) {
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Register ScalarTypeVReg = Type->getOperand(1).getReg();
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SPIRVType *ScalarType = getSPIRVTypeForVReg(ScalarTypeVReg);
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return ScalarType->getOpcode() == TypeOpcode;
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}
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return false;
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}
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unsigned
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SPIRVGlobalRegistry::getScalarOrVectorBitWidth(const SPIRVType *Type) const {
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assert(Type && "Invalid Type pointer");
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if (Type->getOpcode() == SPIRV::OpTypeVector) {
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auto EleTypeReg = Type->getOperand(1).getReg();
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Type = getSPIRVTypeForVReg(EleTypeReg);
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}
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if (Type->getOpcode() == SPIRV::OpTypeInt ||
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Type->getOpcode() == SPIRV::OpTypeFloat)
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return Type->getOperand(1).getImm();
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if (Type->getOpcode() == SPIRV::OpTypeBool)
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return 1;
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llvm_unreachable("Attempting to get bit width of non-integer/float type.");
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}
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bool SPIRVGlobalRegistry::isScalarOrVectorSigned(const SPIRVType *Type) const {
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assert(Type && "Invalid Type pointer");
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if (Type->getOpcode() == SPIRV::OpTypeVector) {
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auto EleTypeReg = Type->getOperand(1).getReg();
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Type = getSPIRVTypeForVReg(EleTypeReg);
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}
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if (Type->getOpcode() == SPIRV::OpTypeInt)
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return Type->getOperand(2).getImm() != 0;
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llvm_unreachable("Attempting to get sign of non-integer type.");
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}
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SPIRV::StorageClass
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SPIRVGlobalRegistry::getPointerStorageClass(Register VReg) const {
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SPIRVType *Type = getSPIRVTypeForVReg(VReg);
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assert(Type && Type->getOpcode() == SPIRV::OpTypePointer &&
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Type->getOperand(1).isImm() && "Pointer type is expected");
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return static_cast<SPIRV::StorageClass>(Type->getOperand(1).getImm());
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}
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SPIRVType *
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SPIRVGlobalRegistry::getOrCreateSPIRVIntegerType(unsigned BitWidth,
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MachineIRBuilder &MIRBuilder) {
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return getOrCreateSPIRVType(
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IntegerType::get(MIRBuilder.getMF().getFunction().getContext(), BitWidth),
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MIRBuilder);
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}
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SPIRVType *SPIRVGlobalRegistry::restOfCreateSPIRVType(Type *LLVMTy,
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MachineInstrBuilder MIB) {
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SPIRVType *SpirvType = MIB;
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VRegToTypeMap[CurMF][getSPIRVTypeID(SpirvType)] = SpirvType;
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SPIRVToLLVMType[SpirvType] = LLVMTy;
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return SpirvType;
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}
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SPIRVType *SPIRVGlobalRegistry::getOrCreateSPIRVIntegerType(
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unsigned BitWidth, MachineInstr &I, const SPIRVInstrInfo &TII) {
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Type *LLVMTy = IntegerType::get(CurMF->getFunction().getContext(), BitWidth);
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MachineBasicBlock &BB = *I.getParent();
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auto MIB = BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpTypeInt))
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.addDef(createTypeVReg(CurMF->getRegInfo()))
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.addImm(BitWidth)
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.addImm(0);
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return restOfCreateSPIRVType(LLVMTy, MIB);
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}
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SPIRVType *
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SPIRVGlobalRegistry::getOrCreateSPIRVBoolType(MachineIRBuilder &MIRBuilder) {
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return getOrCreateSPIRVType(
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IntegerType::get(MIRBuilder.getMF().getFunction().getContext(), 1),
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MIRBuilder);
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}
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SPIRVType *SPIRVGlobalRegistry::getOrCreateSPIRVVectorType(
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SPIRVType *BaseType, unsigned NumElements, MachineIRBuilder &MIRBuilder) {
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return getOrCreateSPIRVType(
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FixedVectorType::get(const_cast<Type *>(getTypeForSPIRVType(BaseType)),
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NumElements),
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MIRBuilder);
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}
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SPIRVType *SPIRVGlobalRegistry::getOrCreateSPIRVVectorType(
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SPIRVType *BaseType, unsigned NumElements, MachineInstr &I,
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const SPIRVInstrInfo &TII) {
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Type *LLVMTy = FixedVectorType::get(
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const_cast<Type *>(getTypeForSPIRVType(BaseType)), NumElements);
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MachineBasicBlock &BB = *I.getParent();
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auto MIB = BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpTypeVector))
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.addDef(createTypeVReg(CurMF->getRegInfo()))
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.addUse(getSPIRVTypeID(BaseType))
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.addImm(NumElements);
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return restOfCreateSPIRVType(LLVMTy, MIB);
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}
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SPIRVType *
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SPIRVGlobalRegistry::getOrCreateSPIRVPointerType(SPIRVType *BaseType,
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MachineIRBuilder &MIRBuilder,
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SPIRV::StorageClass SClass) {
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return getOrCreateSPIRVType(
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PointerType::get(const_cast<Type *>(getTypeForSPIRVType(BaseType)),
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storageClassToAddressSpace(SClass)),
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MIRBuilder);
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|
}
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|
|
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SPIRVType *SPIRVGlobalRegistry::getOrCreateSPIRVPointerType(
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SPIRVType *BaseType, MachineInstr &I, const SPIRVInstrInfo &TII,
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|
SPIRV::StorageClass SC) {
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|
Type *LLVMTy =
|
|
PointerType::get(const_cast<Type *>(getTypeForSPIRVType(BaseType)),
|
|
storageClassToAddressSpace(SC));
|
|
MachineBasicBlock &BB = *I.getParent();
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|
auto MIB = BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpTypePointer))
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|
.addDef(createTypeVReg(CurMF->getRegInfo()))
|
|
.addImm(static_cast<uint32_t>(SC))
|
|
.addUse(getSPIRVTypeID(BaseType));
|
|
return restOfCreateSPIRVType(LLVMTy, MIB);
|
|
}
|