Matt Arsenault 987df725ac AMDGPU: Serialize VGPRForAGPRCopy

2022-04-19 22:14:52 -04:00

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custom-pseudo-source-values.ll

CodeGen: Print/parse LLTs in MachineMemOperands

2021-06-30 16:54:13 -04:00

dead-flag-on-use-operand-parse-error.mir

MIRParser: Fix asserting with invalid flags on machine operands

2022-04-05 21:46:26 -04:00

expected-target-index-name.mir

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extra-imm-operand.mir

MIR: Start diagnosing too many operands on an instruction

2022-02-21 10:36:39 -05:00

extra-reg-operand.mir

MIR: Start diagnosing too many operands on an instruction

2022-02-21 10:36:39 -05:00

intrinsics.mir

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invalid-frame-index2.mir

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invalid-frame-index-invalid-fixed-stack.mir

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invalid-frame-index-invalid-stack.mir

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invalid-frame-index-no-stack.mir

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invalid-frame-index.mir

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invalid-target-index-operand.mir

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killed-flag-on-def-parse-error.mir

MIRParser: Fix asserting with invalid flags on machine operands

2022-04-05 21:46:26 -04:00

lit.local.cfg

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llc-target-cpu-attr-from-cmdline-ir.mir

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llc-target-cpu-attr-from-cmdline.mir

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load-store-opt-dlc.mir

CodeGen: Print/parse LLTs in MachineMemOperands

2021-06-30 16:54:13 -04:00

machine-function-info-after-pei.ll

AMDGPU: Serialize VGPRForAGPRCopy

2022-04-19 22:14:52 -04:00

machine-function-info-dynlds-align-invalid-case.mir

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machine-function-info-no-ir.mir

AMDGPU: Serialize VGPRForAGPRCopy

2022-04-19 22:14:52 -04:00

machine-function-info-register-parse-error1.mir

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machine-function-info-register-parse-error2.mir

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machine-function-info.ll

AMDGPU: Serialize VGPRForAGPRCopy

2022-04-19 22:14:52 -04:00

machine-metadata-error.mir

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machine-metadata.mir

[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range

2022-03-09 12:18:02 +05:30

mfi-frame-offset-reg-class.mir

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mfi-parse-error-frame-offset-reg.mir

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mfi-parse-error-scratch-rsrc-reg.mir

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mfi-parse-error-stack-ptr-offset-reg.mir

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mfi-scratch-rsrc-reg-reg-class.mir

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mfi-stack-ptr-offset-reg-class.mir

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mir-canon-multi.mir

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mircanon-memoperands.mir

CodeGen: Print/parse LLTs in MachineMemOperands

2021-06-30 16:54:13 -04:00

parse-order-reserved-regs.mir

CodeGen: Print/parse LLTs in MachineMemOperands

2021-06-30 16:54:13 -04:00

stack-id-assert.mir

[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range

2022-03-09 12:18:02 +05:30

stack-id.mir

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subreg-def-is-not-ssa.mir

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syncscopes.mir

CodeGen: Print/parse LLTs in MachineMemOperands

2021-06-30 16:54:13 -04:00

target-flags.mir

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target-index-operands.mir

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target-memoperands.mir

[AMDGPU] Use new target MMO flag MONoClobber

2022-02-02 17:12:36 +00:00

vgpr-for-agpr-copy-invalid-reg.mir

AMDGPU: Serialize VGPRForAGPRCopy

2022-04-19 22:14:52 -04:00

wwm-reserved-regs-invalid-reg.mir

AMDGPU: Serialize WWM registers

2022-04-19 21:44:43 -04:00

wwm-reserved-regs-not-a-reg.mir

AMDGPU: Serialize WWM registers

2022-04-19 21:44:43 -04:00

wwm-reserved-regs.mir

AMDGPU: Serialize WWM registers

2022-04-19 21:44:43 -04:00