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llvm-project/llvm/lib/Target/RISCV
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Gábor Spaits 28dd55b973
[RISCV][GISel] Do libcall for G_FPTOSI, G_FPTOUI when no D or F support (#94613) 
When compiling the following code:
```cpp
#include <stdio.h>
#include <stdlib.h>
#include <stddef.h>
#include <stdbool.h>

int main() {
    int a;
    float f;
    scanf("%d", &a);

    scanf("%f", &f);
    a += (int)f;
    
    return a;
}
``` 
for `-march=rv32ima_zbb` we get a libcall:
```
call    scanf
        lw      a0, -20(s0)
        call    __fixsfsi
        mv      a1, a0
```
When we try to use GlobalISel we get this error:
```
 error in backend: unable to legalize instruction: %9:_(s32) = G_FPTOSI %8:_(s32) (in function: main)
```

(Here is a link to a reproducer in Godblot:
https://godbolt.org/z/f67vEEb41 )

The goal of this PR is to do a libcall for the legalization of
`G_FPTOSI` and `G_FPTOUI` instead of doing a fallback to Selection DAG
to do the same libcall later.
2024-06-07 21:27:49 +02:00
..
AsmParser
[RISCV] Codegen support for XCVmem extension (#76916)
2024-06-07 21:45:49 +08:00
Disassembler
[RISCV] Support instruction sizes up to 176-bits in disassembler. (#90371)
2024-04-29 10:11:28 -07:00
GISel
[RISCV][GISel] Do libcall for G_FPTOSI, G_FPTOUI when no D or F support (#94613)
2024-06-07 21:27:49 +02:00
MCA
[RISCV][NFC] Include RISCVVInversePseudosTable in RISCVMCTargetDesc
2024-04-24 09:29:20 -07:00
MCTargetDesc
[RISCV] Move vnclipu patterns into DAGCombiner. (#93596)
2024-05-29 13:00:15 -07:00
TargetInfo
…
CMakeLists.txt
[CodeGen] [ARM] Make RISC-V Init Undef Pass Target Independent and add support for the ARM Architecture. (#77770)
2024-02-26 12:12:31 +00:00
RISCV.h
Reland "[NewPM][CodeGen] Port selection dag isel to new pass manager" (#94149)
2024-06-04 08:10:58 +08:00
RISCV.td
[RISCV] Add subtarget features for profiles
2024-04-28 11:32:37 +08:00
RISCVAsmPrinter.cpp
[RISCV] Split code that tablegen needs out of RISCVISAInfo. (#89684)
2024-04-23 15:12:36 -07:00
RISCVCallingConv.td
[RISCV] RISCV vector calling convention (1/2) (#77560)
2024-03-27 23:03:13 +08:00
RISCVCodeGenPrepare.cpp
[RISCV] Don't look for sext in RISCVCodeGenPrepare::visitAnd.
2024-01-19 14:44:47 -08:00
RISCVCombine.td
…
RISCVDeadRegisterDefinitions.cpp
[RISCV] Remove hasSideEffects=1 for vsetvli pseudos (#91319)
2024-05-15 23:37:31 +08:00
RISCVExpandAtomicPseudoInsts.cpp
…
RISCVExpandPseudoInsts.cpp
[RISCV] Re-separate unaligned scalar and vector memory features in the backend. (#88954)
2024-04-16 15:40:32 -07:00
RISCVFeatures.td
[RISCV] Remove experimental from Zabha (#93831)
2024-06-03 17:27:02 +08:00
RISCVFoldMasks.cpp
[RISCV] Use DenseMap to track V0 definition. NFC (#84465)
2024-03-21 15:38:43 +08:00
RISCVFrameLowering.cpp
[RISCV] Add X27 to SavedRegs when X26 is in SavedRegs for cm.push/pop (#92067)
2024-05-14 08:06:10 -07:00
RISCVFrameLowering.h
[RISCV] Add CFI information for vector callee-saved registers (#86811)
2024-04-17 10:42:40 +08:00
RISCVGatherScatterLowering.cpp
[RISCV] Match strided vector bases in RISCVGatherScatterLowering (#93972)
2024-06-03 11:12:27 +01:00
RISCVGISel.td
…
RISCVInsertReadWriteCSR.cpp
[CodeGen] Make the parameter TRI required in some functions. (#85968)
2024-04-24 14:24:14 +01:00
RISCVInsertVSETVLI.cpp
[RISCV][InsertVSETVLI] Check for undef register operand directly [nfc]
2024-06-06 13:21:04 -07:00
RISCVInsertWriteVXRM.cpp
[CodeGen] Make the parameter TRI required in some functions. (#85968)
2024-04-24 14:24:14 +01:00
RISCVInstrFormats.td
[RISCV] Rename OP-P to OP-VE. (#87546)
2024-04-05 17:02:03 -07:00
RISCVInstrFormatsC.td
…
RISCVInstrFormatsV.td
…
RISCVInstrGISel.td
[RISCV][GISEL] Legalize G_ZEXT, G_SEXT, and G_ANYEXT, G_SPLAT_VECTOR, and G_ICMP for scalable vector types
2024-04-03 15:27:15 -07:00
RISCVInstrInfo.cpp
[RISCV] Codegen support for XCVbi extension (#89719)
2024-05-08 11:22:16 +08:00
RISCVInstrInfo.h
[RISCV] Codegen support for XCVbi extension (#89719)
2024-05-08 11:22:16 +08:00
RISCVInstrInfo.td
[RISCV] Add .insn alias for addresses without the leading immediate. (#94698)
2024-06-07 10:07:47 -07:00
RISCVInstrInfoA.td
[RISCV] Remove mayLoad = 1 from store-conditional (#88470)
2024-04-12 08:45:47 -07:00
RISCVInstrInfoC.td
[RISCV] Add .insn alias for addresses without the leading immediate. (#94698)
2024-06-07 10:07:47 -07:00
RISCVInstrInfoD.td
[RISCV] Use REG_SEQUENCE/EXTRACT_SUBREG to move between individual GPRs and GPRPair. (#85887)
2024-03-20 08:44:24 -07:00
RISCVInstrInfoF.td
[RISCV] Add casts to isel patterns that produce more than 1 instruction.
2024-02-08 23:38:19 -08:00
RISCVInstrInfoM.td
[RISCV] Split div vs rem scheduling information [nfc] (#84385)
2024-03-07 14:03:58 -08:00
RISCVInstrInfoSFB.td
[RISCV][NFC] Move SFB pseudos and patterns to RISCVInstrInfoSFB.td (#80945)
2024-02-07 16:03:30 +08:00
RISCVInstrInfoV.td
[RISCV] Split sched classes for vrgather.vv and vrgatherei16.vv (#92768)
2024-05-23 12:10:46 -04:00
RISCVInstrInfoVPseudos.td
Reland "[RISCV] Support select/merge like ops for bf16 vectors when have Zvfbfmin" (#94565)"
2024-06-07 15:55:16 +08:00
RISCVInstrInfoVSDPatterns.td
Reland "[RISCV] Support select/merge like ops for bf16 vectors when have Zvfbfmin" (#94565)"
2024-06-07 15:55:16 +08:00
RISCVInstrInfoVVLPatterns.td
Reland "[RISCV] Support select/merge like ops for bf16 vectors when have Zvfbfmin" (#94565)"
2024-06-07 15:55:16 +08:00
RISCVInstrInfoXCV.td
[RISCV] Codegen support for XCVmem extension (#76916)
2024-06-07 21:45:49 +08:00
RISCVInstrInfoXSf.td
[RISCV] Add scheduling information for SiFive VCIX (#86093)
2024-04-16 13:55:45 +08:00
RISCVInstrInfoXTHead.td
[RISCV] Move strength reduction of mul X, 3/5/9*2^N to combine (#89966)
2024-05-08 10:13:01 -07:00
RISCVInstrInfoXVentana.td
…
RISCVInstrInfoZa.td
[RISCV][ISel] Add codegen support for the experimental zabha extension (#80192)
2024-02-16 15:35:09 +08:00
RISCVInstrInfoZalasr.td
[RISCV][MC] MC layer support for the experimental zalasr extension (#79911)
2024-02-01 10:58:21 -08:00
RISCVInstrInfoZb.td
[RISCV] Move strength reduction of mul X, 3/5/9*2^N to combine (#89966)
2024-05-08 10:13:01 -07:00
RISCVInstrInfoZc.td
[RISCV] Add validation of SPIMM for cm.push/pop. (#84989)
2024-03-28 08:38:18 -07:00
RISCVInstrInfoZcmop.td
[RISCV] Correct the spelling of the Zcmop mnemonics. (#88826)
2024-04-15 22:33:14 -07:00
RISCVInstrInfoZfa.td
…
RISCVInstrInfoZfbfmin.td
…
RISCVInstrInfoZfh.td
[RISCV] Add casts to isel patterns that produce more than 1 instruction.
2024-02-08 23:38:19 -08:00
RISCVInstrInfoZicbo.td
…
RISCVInstrInfoZicfiss.td
[RISCV] Add MC layer support for Zicfiss. (#66043)
2023-12-30 15:40:20 +08:00
RISCVInstrInfoZicond.td
[RISCV] Graduate Zicond to non-experimental (#79811)
2024-01-29 15:58:54 +00:00
RISCVInstrInfoZimop.td
[RISCV] Zimop/Zcmop are ratified
2024-04-08 16:40:02 +08:00
RISCVInstrInfoZk.td
…
RISCVInstrInfoZvfbf.td
…
RISCVInstrInfoZvk.td
[RISCV] Add Sched classes for vector crypto instructions (#90068)
2024-05-03 11:11:29 -04:00
RISCVISelDAGToDAG.cpp
[RISCV] Codegen support for XCVmem extension (#76916)
2024-06-07 21:45:49 +08:00
RISCVISelDAGToDAG.h
[RISCV] Codegen support for XCVmem extension (#76916)
2024-06-07 21:45:49 +08:00
RISCVISelLowering.cpp
[RISCV] Fold (vXi8 (trunc (vselect (setltu, X, 256), X, (sext (setgt X, 0))))) to vmax+vnclipu. (#94720)
2024-06-07 09:57:03 -07:00
RISCVISelLowering.h
[RISCV] Move vnclipu patterns into DAGCombiner. (#93596)
2024-05-29 13:00:15 -07:00
RISCVMachineFunctionInfo.cpp
…
RISCVMachineFunctionInfo.h
…
RISCVMacroFusion.td
[RISCV] Use TableGen-based macro fusion (#72224)
2024-01-25 17:10:49 +08:00
RISCVMakeCompressible.cpp
[RISCV] Teach RISCVMakeCompressible handle byte/half load/store for Zcb. (#83375)
2024-03-27 13:40:38 +08:00
RISCVMergeBaseOffset.cpp
[RISCV] Add a rematerializable pseudo instruction for LUI+ADDI for global addresses. (#93352)
2024-05-28 15:05:23 -07:00
RISCVMoveMerger.cpp
[RISCV] Cleanup pass initialization.
2023-12-07 18:21:38 -08:00
RISCVOptWInstrs.cpp
[CodeGen] Make the parameter TRI required in some functions. (#85968)
2024-04-24 14:24:14 +01:00
RISCVPostRAExpandPseudoInsts.cpp
[RISCV] Add a rematerializable pseudo instruction for LUI+ADDI for global addresses. (#93352)
2024-05-28 15:05:23 -07:00
RISCVProcessors.td
[RISCV] Do not check PostRAScheduler in enablePostRAScheduler (#92781)
2024-05-24 14:31:14 -04:00
RISCVProfiles.td
[RISCV] Gate unratified profiles behind -menable-experimental-extensions (#92167)
2024-05-15 21:09:43 +01:00
RISCVPushPopOptimizer.cpp
[RISCV] Add correct Uses, Defs, isReturn to Zcmp (#81039)
2024-02-07 14:30:45 -08:00
RISCVRedundantCopyElimination.cpp
[RISCV] Codegen support for XCVbi extension (#89719)
2024-05-08 11:22:16 +08:00
RISCVRegisterInfo.cpp
[RISCV] Inogre CallingConv::RISCV_VectorCall in getCalleeSavedRegs if V/Zve is not enabled.
2024-05-13 16:04:09 -07:00
RISCVRegisterInfo.h
[RISCV] Store VLMul/NF into RegisterClass's TSFlags
2024-04-08 13:35:37 +08:00
RISCVRegisterInfo.td
[RISCV] Use software guarded branch for indirect jump table branch. (#66762)
2024-05-14 14:44:25 +08:00
RISCVSchedRocket.td
[RISCV] Add Sched classes for vector crypto instructions (#90068)
2024-05-03 11:11:29 -04:00
RISCVSchedSiFive7.td
[RISCV] Do not check PostRAScheduler in enablePostRAScheduler (#92781)
2024-05-24 14:31:14 -04:00
RISCVSchedSiFiveP400.td
[RISCV] Adjust FP load latencies from 6 to 5 in SiFiveP400/P600 scheduling models (#93735)
2024-05-30 08:47:27 -07:00
RISCVSchedSiFiveP600.td
[RISCV] Adjust FP load latencies from 6 to 5 in SiFiveP400/P600 scheduling models (#93735)
2024-05-30 08:47:27 -07:00
RISCVSchedSyntacoreSCR1.td
[RISCV] Add Sched classes for vector crypto instructions (#90068)
2024-05-03 11:11:29 -04:00
RISCVSchedule.td
[RISCV] Add Sched classes for vector crypto instructions (#90068)
2024-05-03 11:11:29 -04:00
RISCVScheduleV.td
[RISCV] Split sched classes for vrgather.vv and vrgatherei16.vv (#92768)
2024-05-23 12:10:46 -04:00
RISCVScheduleXSf.td
[RISCV] Add scheduling information for SiFive VCIX (#86093)
2024-04-16 13:55:45 +08:00
RISCVScheduleZb.td
[RISCV] Add sched classes for Zbb integer min max instructions
2024-03-14 06:02:42 -07:00
RISCVScheduleZvk.td
[RISCV] Add Sched classes for vector crypto instructions (#90068)
2024-05-03 11:11:29 -04:00
RISCVSchedXiangShanNanHu.td
[RISCV] Add Sched classes for vector crypto instructions (#90068)
2024-05-03 11:11:29 -04:00
RISCVSubtarget.cpp
[RISCV] Use TableGen-based macro fusion (#72224)
2024-01-25 17:10:49 +08:00
RISCVSubtarget.h
[RISCV] Do not check PostRAScheduler in enablePostRAScheduler (#92781)
2024-05-24 14:31:14 -04:00
RISCVSystemOperands.td
[RISCV] Add the CSR names from Smrnmi. (#83370)
2024-03-19 21:27:25 -07:00
RISCVTargetMachine.cpp
Reland "[NewPM][CodeGen] Port selection dag isel to new pass manager" (#94149)
2024-06-04 08:10:58 +08:00
RISCVTargetMachine.h
…
RISCVTargetObjectFile.cpp
[RISCV] Place mergeable small read only data into srodata section (#82214)
2024-03-11 13:57:06 +08:00
RISCVTargetObjectFile.h
[RISCV] Place mergeable small read only data into srodata section (#82214)
2024-03-11 13:57:06 +08:00
RISCVTargetTransformInfo.cpp
[RISCV][LSR] Account for temporary register for base addition (#92296)
2024-05-22 13:38:39 -07:00
RISCVTargetTransformInfo.h
[TTI] getArithmeticInstrCost - use std:nullopt to create default empty ArrayRef<const Value *> Args argument. NFC.
2024-04-24 10:51:18 +01:00