0605e984fa
Prior to this change, `SelectionDAGBuilder` was producing `SDNode`s of the form: `f32 = extract_vector_elt <1 x bfloat|half>, i32 0` when lowering phis of `<1 x bfloat|half>` and running on a target that promotes this type to `f32` (like some x86 or AMDGPU targets.) This construct is invalid since this type of node only allows type extensions for integer types. It went unotice because the `extract_vector_elt` node is later broken down in `bitcast` followed by `bf16_to_fp|fp_extend`. However, when the argument of the phi is a constant we were crashing because the existing code would try to constant fold this `extract_vector_elt` into a any_ext. This patch fixes this by using a proper decomposition for `<1 x bfloat|half>`: ``` bfloat|half = bitcast <1 x blfoat|half> float = fp_extend bfloat|half ``` This change should be NFC for the non-constant-folding cases and fix the SDISel crashes (reported in https://github.com/llvm/llvm-project/issues/94449) for the folding cases. Note: The change on the arm test is a missing fp16 to f32 constant folding exposed by this patch. I'll push a separate improvement for that.
139 lines
5.3 KiB
LLVM
139 lines
5.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdpal -mcpu=hawaii %s -o - | FileCheck %s
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; For all these tests we disable optimizations through function attributes
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; because the code we are exercising here needs phis and we want to keep the
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; IR small.
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; This code used to crash in SDISel because f16 was promoted to f32 through
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; a `f32 = vector_extract_elt <1 x f16>, i32 0`, which is illegal.
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; The invalid SDNode and thus, the crash was only exposed by the constant
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; folding.
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define void @phi_vec1half_to_f32_with_const_folding(ptr addrspace(1) %dst) #0 {
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; CHECK-LABEL: phi_vec1half_to_f32_with_const_folding:
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; CHECK: ; %bb.0: ; %entry
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; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CHECK-NEXT: s_mov_b32 s4, 0
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; CHECK-NEXT: v_cvt_f32_f16_e64 v2, s4
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; CHECK-NEXT: ; %bb.1: ; %bb
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; CHECK-NEXT: v_cvt_f16_f32_e64 v2, v2
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; CHECK-NEXT: s_mov_b32 s7, 0xf000
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; CHECK-NEXT: s_mov_b32 s6, 0
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; CHECK-NEXT: s_mov_b32 s4, s6
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; CHECK-NEXT: s_mov_b32 s5, s6
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; CHECK-NEXT: buffer_store_short v2, v[0:1], s[4:7], 0 addr64 offset:2
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; CHECK-NEXT: v_cvt_f16_f32_e64 v2, s4
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; CHECK-NEXT: buffer_store_short v2, v[0:1], s[4:7], 0 addr64
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; CHECK-NEXT: s_waitcnt vmcnt(0)
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; CHECK-NEXT: s_setpc_b64 s[30:31]
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entry:
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br label %bb
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bb:
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%phi = phi <1 x half> [ zeroinitializer, %entry ]
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%res = shufflevector <1 x half> poison, <1 x half> %phi, <2 x i32> <i32 0, i32 1>
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store <2 x half> %res, ptr addrspace(1) %dst
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ret void
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}
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; Same as phi_vec1half_to_f32_with_const_folding but without the folding.
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; This test exercises the same invalid SDNode, but it happened to work by
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; accident before. Here we make sure the fix also work as expected in the
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; non-constant folding case.
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define void @phi_vec1half_to_f32(ptr addrspace(1) %src, ptr addrspace(1) %dst) #0 {
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; CHECK-LABEL: phi_vec1half_to_f32:
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; CHECK: ; %bb.0: ; %entry
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; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CHECK-NEXT: s_mov_b32 s7, 0xf000
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; CHECK-NEXT: s_mov_b32 s6, 0
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; CHECK-NEXT: s_mov_b32 s4, s6
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; CHECK-NEXT: s_mov_b32 s5, s6
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; CHECK-NEXT: buffer_load_ushort v0, v[0:1], s[4:7], 0 addr64
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; CHECK-NEXT: s_waitcnt vmcnt(0)
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; CHECK-NEXT: v_cvt_f32_f16_e64 v0, v0
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; CHECK-NEXT: ; %bb.1: ; %bb
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; CHECK-NEXT: v_cvt_f16_f32_e64 v0, v0
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; CHECK-NEXT: s_mov_b32 s7, 0xf000
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; CHECK-NEXT: s_mov_b32 s6, 0
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; CHECK-NEXT: s_mov_b32 s4, s6
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; CHECK-NEXT: s_mov_b32 s5, s6
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; CHECK-NEXT: buffer_store_short v0, v[2:3], s[4:7], 0 addr64 offset:2
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; CHECK-NEXT: v_cvt_f16_f32_e64 v0, s4
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; CHECK-NEXT: buffer_store_short v0, v[2:3], s[4:7], 0 addr64
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; CHECK-NEXT: s_waitcnt vmcnt(0)
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; CHECK-NEXT: s_setpc_b64 s[30:31]
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entry:
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%input = load <1 x half>, ptr addrspace(1) %src
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br label %bb
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bb:
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%phi = phi <1 x half> [ %input, %entry ]
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%res = shufflevector <1 x half> poison, <1 x half> %phi, <2 x i32> <i32 0, i32 1>
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store <2 x half> %res, ptr addrspace(1) %dst
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ret void
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}
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; Same as phi_vec1bf16_to_f32 but with bfloat instead of half.
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define void @phi_vec1bf16_to_f32(ptr addrspace(1) %src, ptr addrspace(1) %dst) #0 {
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; CHECK-LABEL: phi_vec1bf16_to_f32:
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; CHECK: ; %bb.0: ; %entry
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; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CHECK-NEXT: s_mov_b32 s7, 0xf000
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; CHECK-NEXT: s_mov_b32 s6, 0
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; CHECK-NEXT: s_mov_b32 s4, s6
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; CHECK-NEXT: s_mov_b32 s5, s6
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; CHECK-NEXT: buffer_load_ushort v0, v[0:1], s[4:7], 0 addr64
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; CHECK-NEXT: s_mov_b32 s4, 16
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; CHECK-NEXT: s_waitcnt vmcnt(0)
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; CHECK-NEXT: v_lshlrev_b32_e64 v0, s4, v0
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; CHECK-NEXT: ; %bb.1: ; %bb
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; CHECK-NEXT: v_mul_f32_e64 v0, 1.0, v0
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; CHECK-NEXT: s_mov_b32 s4, 16
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; CHECK-NEXT: v_lshrrev_b32_e64 v0, s4, v0
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; CHECK-NEXT: s_mov_b32 s7, 0xf000
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; CHECK-NEXT: s_mov_b32 s6, 0
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; CHECK-NEXT: s_mov_b32 s4, s6
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; CHECK-NEXT: s_mov_b32 s5, s6
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; CHECK-NEXT: buffer_store_short v0, v[2:3], s[4:7], 0 addr64 offset:2
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; CHECK-NEXT: s_waitcnt vmcnt(0)
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; CHECK-NEXT: s_setpc_b64 s[30:31]
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entry:
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%input = load <1 x bfloat>, ptr addrspace(1) %src
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br label %bb
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bb:
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%phi = phi <1 x bfloat> [ %input, %entry ]
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%res = shufflevector <1 x bfloat> poison, <1 x bfloat> %phi, <2 x i32> <i32 0, i32 1>
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store <2 x bfloat> %res, ptr addrspace(1) %dst
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ret void
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}
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; Same as phi_vec1half_to_f32_with_const_folding but with bfloat instead of half.
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define void @phi_vec1bf16_to_f32_with_const_folding(ptr addrspace(1) %dst) #0 {
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; CHECK-LABEL: phi_vec1bf16_to_f32_with_const_folding:
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; CHECK: ; %bb.0: ; %entry
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; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CHECK-NEXT: s_mov_b32 s4, 0
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; CHECK-NEXT: ; %bb.1: ; %bb
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; CHECK-NEXT: v_mul_f32_e64 v2, 1.0, s4
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; CHECK-NEXT: s_mov_b32 s4, 16
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; CHECK-NEXT: v_lshrrev_b32_e32 v2, s4, v2
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; CHECK-NEXT: s_mov_b32 s7, 0xf000
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; CHECK-NEXT: s_mov_b32 s6, 0
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; CHECK-NEXT: s_mov_b32 s4, s6
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; CHECK-NEXT: s_mov_b32 s5, s6
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; CHECK-NEXT: buffer_store_short v2, v[0:1], s[4:7], 0 addr64 offset:2
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; CHECK-NEXT: s_waitcnt vmcnt(0)
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; CHECK-NEXT: s_setpc_b64 s[30:31]
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entry:
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br label %bb
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bb:
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%phi = phi <1 x bfloat> [ zeroinitializer, %entry ]
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%res = shufflevector <1 x bfloat> poison, <1 x bfloat> %phi, <2 x i32> <i32 0, i32 1>
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store <2 x bfloat> %res, ptr addrspace(1) %dst
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ret void
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}
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attributes #0 = { noinline optnone }
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