bfb953926c
Allow a target to steal the definition of a generic pseudoinstruction and remap the operands. This works by defining a new instruction, which will simply swap out the emitted entry in the InstrInfo table. This is intended to eliminate the C++ half of the implementation of PointerLikeRegClass. With RegClassByHwMode, the remaining usecase for PointerLikeRegClass are the common codegen pseudoinstructions. Every target maintains its own copy of the generic pseudo operand definitions anyway, so we can stub out the register operands with an appropriate class instead of waiting for runtime resolution. In the future we could probably take this a bit further. For example, there is a similar problem for ADJCALLSTACKUP/DOWN since they depend on target register definitions for the stack pointer register.
428 lines
15 KiB
C++
428 lines
15 KiB
C++
//===- CodeGenTarget.cpp - CodeGen Target Class Wrapper -------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This class wraps target description classes used by the various code
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// generation TableGen backends. This makes it easier to access the data and
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// provides a single place that needs to check it for validity. All of these
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// classes abort on error conditions.
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//
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//===----------------------------------------------------------------------===//
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#include "CodeGenTarget.h"
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#include "CodeGenInstruction.h"
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#include "CodeGenRegisters.h"
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#include "CodeGenSchedule.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/ADT/Twine.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/TableGen/Error.h"
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#include "llvm/TableGen/Record.h"
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#include <tuple>
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using namespace llvm;
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static cl::OptionCategory AsmParserCat("Options for -gen-asm-parser");
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static cl::OptionCategory AsmWriterCat("Options for -gen-asm-writer");
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static cl::opt<unsigned>
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AsmParserNum("asmparsernum", cl::init(0),
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cl::desc("Make -gen-asm-parser emit assembly parser #N"),
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cl::cat(AsmParserCat));
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static cl::opt<unsigned>
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AsmWriterNum("asmwriternum", cl::init(0),
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cl::desc("Make -gen-asm-writer emit assembly writer #N"),
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cl::cat(AsmWriterCat));
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/// getValueType - Return the MVT::SimpleValueType that the specified TableGen
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/// record corresponds to.
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MVT::SimpleValueType llvm::getValueType(const Record *Rec) {
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return (MVT::SimpleValueType)Rec->getValueAsInt("Value");
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}
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StringRef llvm::getEnumName(MVT::SimpleValueType T) {
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// clang-format off
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switch (T) {
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#define GET_VT_ATTR(Ty, N, Sz, Any, Int, FP, Vec, Sc, Tup, NF, NElem, EltTy) \
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case MVT::Ty: return "MVT::" # Ty;
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#include "llvm/CodeGen/GenVT.inc"
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default: llvm_unreachable("ILLEGAL VALUE TYPE!");
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}
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// clang-format on
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}
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/// getQualifiedName - Return the name of the specified record, with a
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/// namespace qualifier if the record contains one.
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///
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std::string llvm::getQualifiedName(const Record *R) {
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std::string Namespace;
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if (R->getValue("Namespace"))
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Namespace = R->getValueAsString("Namespace").str();
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if (Namespace.empty())
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return R->getName().str();
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return Namespace + "::" + R->getName().str();
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}
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CodeGenTarget::CodeGenTarget(const RecordKeeper &records)
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: Records(records), CGH(records), Intrinsics(records) {
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ArrayRef<const Record *> Targets = Records.getAllDerivedDefinitions("Target");
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if (Targets.size() == 0)
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PrintFatalError("No 'Target' subclasses defined!");
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if (Targets.size() != 1)
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PrintFatalError("Multiple subclasses of Target defined!");
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TargetRec = Targets[0];
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MacroFusions = Records.getAllDerivedDefinitions("Fusion");
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}
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CodeGenTarget::~CodeGenTarget() = default;
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StringRef CodeGenTarget::getName() const { return TargetRec->getName(); }
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/// getInstNamespace - Find and return the target machine's instruction
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/// namespace. The namespace is cached because it is requested multiple times.
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StringRef CodeGenTarget::getInstNamespace() const {
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if (InstNamespace.empty()) {
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for (const CodeGenInstruction *Inst : getInstructions()) {
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// We are not interested in the "TargetOpcode" namespace.
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if (Inst->Namespace != "TargetOpcode") {
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InstNamespace = Inst->Namespace;
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break;
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}
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}
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}
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return InstNamespace;
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}
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StringRef CodeGenTarget::getRegNamespace() const {
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auto &RegClasses = RegBank->getRegClasses();
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return RegClasses.size() > 0 ? RegClasses.front().Namespace : "";
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}
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const Record *CodeGenTarget::getInstructionSet() const {
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return TargetRec->getValueAsDef("InstructionSet");
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}
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bool CodeGenTarget::getAllowRegisterRenaming() const {
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return TargetRec->getValueAsInt("AllowRegisterRenaming");
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}
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/// getAsmParser - Return the AssemblyParser definition for this target.
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///
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const Record *CodeGenTarget::getAsmParser() const {
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std::vector<const Record *> LI =
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TargetRec->getValueAsListOfDefs("AssemblyParsers");
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if (AsmParserNum >= LI.size())
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PrintFatalError("Target does not have an AsmParser #" +
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Twine(AsmParserNum) + "!");
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return LI[AsmParserNum];
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}
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/// getAsmParserVariant - Return the AssemblyParserVariant definition for
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/// this target.
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///
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const Record *CodeGenTarget::getAsmParserVariant(unsigned Idx) const {
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std::vector<const Record *> LI =
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TargetRec->getValueAsListOfDefs("AssemblyParserVariants");
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if (Idx >= LI.size())
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PrintFatalError("Target does not have an AsmParserVariant #" + Twine(Idx) +
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"!");
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return LI[Idx];
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}
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/// getAsmParserVariantCount - Return the AssemblyParserVariant definition
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/// available for this target.
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///
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unsigned CodeGenTarget::getAsmParserVariantCount() const {
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return TargetRec->getValueAsListOfDefs("AssemblyParserVariants").size();
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}
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/// getAsmWriter - Return the AssemblyWriter definition for this target.
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///
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const Record *CodeGenTarget::getAsmWriter() const {
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std::vector<const Record *> LI =
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TargetRec->getValueAsListOfDefs("AssemblyWriters");
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if (AsmWriterNum >= LI.size())
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PrintFatalError("Target does not have an AsmWriter #" +
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Twine(AsmWriterNum) + "!");
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return LI[AsmWriterNum];
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}
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CodeGenRegBank &CodeGenTarget::getRegBank() const {
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if (!RegBank)
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RegBank = std::make_unique<CodeGenRegBank>(Records, getHwModes());
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return *RegBank;
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}
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/// getRegisterByName - If there is a register with the specific AsmName,
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/// return it.
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const CodeGenRegister *CodeGenTarget::getRegisterByName(StringRef Name) const {
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return getRegBank().getRegistersByName().lookup(Name);
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}
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const CodeGenRegisterClass &
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CodeGenTarget::getRegisterClass(const Record *R) const {
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return *getRegBank().getRegClass(R);
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}
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std::vector<ValueTypeByHwMode>
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CodeGenTarget::getRegisterVTs(const Record *R) const {
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const CodeGenRegister *Reg = getRegBank().getReg(R);
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std::vector<ValueTypeByHwMode> Result;
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for (const auto &RC : getRegBank().getRegClasses()) {
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if (RC.contains(Reg)) {
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ArrayRef<ValueTypeByHwMode> InVTs = RC.getValueTypes();
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llvm::append_range(Result, InVTs);
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}
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}
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// Remove duplicates.
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llvm::sort(Result);
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Result.erase(llvm::unique(Result), Result.end());
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return Result;
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}
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void CodeGenTarget::ReadLegalValueTypes() const {
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for (const auto &RC : getRegBank().getRegClasses())
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llvm::append_range(LegalValueTypes, RC.VTs);
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// Remove duplicates.
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llvm::sort(LegalValueTypes);
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LegalValueTypes.erase(llvm::unique(LegalValueTypes), LegalValueTypes.end());
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}
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const Record *CodeGenTarget::getInitValueAsRegClass(
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const Init *V, bool AssumeRegClassByHwModeIsDefault) const {
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const Record *RegClassLike = getInitValueAsRegClassLike(V);
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if (!RegClassLike || RegClassLike->isSubClassOf("RegisterClass"))
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return RegClassLike;
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// FIXME: We should figure out the hwmode and dispatch. But this interface
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// is broken, we should be returning a register class. The expected uses
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// will use the same RegBanks in all modes.
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if (AssumeRegClassByHwModeIsDefault &&
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RegClassLike->isSubClassOf("RegClassByHwMode")) {
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const HwModeSelect &ModeSelect = getHwModes().getHwModeSelect(RegClassLike);
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if (ModeSelect.Items.empty())
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return nullptr;
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return ModeSelect.Items.front().second;
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}
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return nullptr;
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}
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const Record *CodeGenTarget::getInitValueAsRegClassLike(const Init *V) const {
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const DefInit *VDefInit = dyn_cast<DefInit>(V);
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if (!VDefInit)
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return nullptr;
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const Record *RegClass = VDefInit->getDef();
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if (RegClass->isSubClassOf("RegisterOperand"))
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return RegClass->getValueAsDef("RegClass");
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return RegClass->isSubClassOf("RegisterClassLike") ? RegClass : nullptr;
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}
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CodeGenSchedModels &CodeGenTarget::getSchedModels() const {
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if (!SchedModels)
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SchedModels = std::make_unique<CodeGenSchedModels>(Records, *this);
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return *SchedModels;
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}
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void CodeGenTarget::ReadInstructions() const {
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ArrayRef<const Record *> Insts =
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Records.getAllDerivedDefinitions("Instruction");
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if (Insts.size() <= 2)
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PrintFatalError("No 'Instruction' subclasses defined!");
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// Parse the instructions defined in the .td file.
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for (const Record *R : Insts) {
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auto [II, _] =
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InstructionMap.try_emplace(R, std::make_unique<CodeGenInstruction>(R));
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HasVariableLengthEncodings |= II->second->isVariableLengthEncoding();
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}
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}
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static const CodeGenInstruction *GetInstByName(
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StringRef Name,
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const DenseMap<const Record *, std::unique_ptr<CodeGenInstruction>> &Insts,
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const RecordKeeper &Records) {
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const Record *Rec = Records.getDef(Name);
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const auto I = Insts.find(Rec);
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if (!Rec || I == Insts.end())
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PrintFatalError("Could not find '" + Name + "' instruction!");
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return I->second.get();
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}
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static const char *FixedInstrs[] = {
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#define HANDLE_TARGET_OPCODE(OPC) #OPC,
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#include "llvm/Support/TargetOpcodes.def"
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};
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unsigned CodeGenTarget::getNumFixedInstructions() {
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return std::size(FixedInstrs);
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}
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/// Return all of the instructions defined by the target, ordered by
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/// their enum value.
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void CodeGenTarget::ComputeInstrsByEnum() const {
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const auto &InstMap = getInstructionMap();
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for (const char *Name : FixedInstrs) {
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const CodeGenInstruction *Instr = GetInstByName(Name, InstMap, Records);
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assert(Instr && "Missing target independent instruction");
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assert(Instr->Namespace == "TargetOpcode" && "Bad namespace");
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InstrsByEnum.push_back(Instr);
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}
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unsigned EndOfPredefines = InstrsByEnum.size();
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assert(EndOfPredefines == getNumFixedInstructions() &&
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"Missing generic opcode");
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unsigned SkippedInsts = 0;
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for (const auto &[_, CGIUp] : InstMap) {
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const CodeGenInstruction *CGI = CGIUp.get();
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if (CGI->Namespace != "TargetOpcode") {
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if (CGI->TheDef->isSubClassOf(
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"TargetSpecializedStandardPseudoInstruction")) {
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++SkippedInsts;
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continue;
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}
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InstrsByEnum.push_back(CGI);
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NumPseudoInstructions += CGI->TheDef->getValueAsBit("isPseudo");
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}
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}
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assert(InstrsByEnum.size() + SkippedInsts == InstMap.size() &&
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"Missing predefined instr");
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// All of the instructions are now in random order based on the map iteration.
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llvm::sort(
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InstrsByEnum.begin() + EndOfPredefines, InstrsByEnum.end(),
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[](const CodeGenInstruction *Rec1, const CodeGenInstruction *Rec2) {
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const Record &D1 = *Rec1->TheDef;
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const Record &D2 = *Rec2->TheDef;
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// Sort all pseudo instructions before non-pseudo ones, and sort by name
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// within.
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return std::tuple(!Rec1->isPseudo, D1.getName()) <
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std::tuple(!Rec2->isPseudo, D2.getName());
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});
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// Assign an enum value to each instruction according to the sorted order.
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for (const auto &[Idx, Inst] : enumerate(InstrsByEnum))
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Inst->EnumVal = Idx;
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}
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/// isLittleEndianEncoding - Return whether this target encodes its instruction
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/// in little-endian format, i.e. bits laid out in the order [0..n]
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///
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bool CodeGenTarget::isLittleEndianEncoding() const {
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return getInstructionSet()->getValueAsBit("isLittleEndianEncoding");
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}
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/// reverseBitsForLittleEndianEncoding - For little-endian instruction bit
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/// encodings, reverse the bit order of all instructions.
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void CodeGenTarget::reverseBitsForLittleEndianEncoding() {
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if (!isLittleEndianEncoding())
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return;
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for (const Record *R :
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Records.getAllDerivedDefinitions("InstructionEncoding")) {
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if (R->getValueAsString("Namespace") == "TargetOpcode" ||
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R->getValueAsBit("isPseudo"))
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continue;
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const BitsInit *BI = R->getValueAsBitsInit("Inst");
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unsigned numBits = BI->getNumBits();
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SmallVector<const Init *, 16> NewBits(numBits);
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for (unsigned bit = 0, end = numBits / 2; bit != end; ++bit) {
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unsigned bitSwapIdx = numBits - bit - 1;
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const Init *OrigBit = BI->getBit(bit);
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const Init *BitSwap = BI->getBit(bitSwapIdx);
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NewBits[bit] = BitSwap;
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NewBits[bitSwapIdx] = OrigBit;
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}
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if (numBits % 2) {
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unsigned middle = (numBits + 1) / 2;
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NewBits[middle] = BI->getBit(middle);
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}
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RecordKeeper &MutableRC = const_cast<RecordKeeper &>(Records);
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const BitsInit *NewBI = BitsInit::get(MutableRC, NewBits);
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// Update the bits in reversed order so that emitters will get the correct
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// endianness.
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// FIXME: Eliminate mutation of TG records by creating a helper function
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// to reverse bits and maintain a cache instead of mutating records.
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Record *MutableR = const_cast<Record *>(R);
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MutableR->getValue("Inst")->setValue(NewBI);
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}
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}
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/// guessInstructionProperties - Return true if it's OK to guess instruction
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/// properties instead of raising an error.
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///
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/// This is configurable as a temporary migration aid. It will eventually be
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/// permanently false.
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bool CodeGenTarget::guessInstructionProperties() const {
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return getInstructionSet()->getValueAsBit("guessInstructionProperties");
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}
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//===----------------------------------------------------------------------===//
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// ComplexPattern implementation
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//
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ComplexPattern::ComplexPattern(const Record *R) {
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Ty = R->getValueAsDef("Ty");
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NumOperands = R->getValueAsInt("NumOperands");
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SelectFunc = R->getValueAsString("SelectFunc").str();
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RootNodes = R->getValueAsListOfDefs("RootNodes");
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// FIXME: This is a hack to statically increase the priority of patterns which
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// maps a sub-dag to a complex pattern. e.g. favors LEA over ADD. To get best
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// possible pattern match we'll need to dynamically calculate the complexity
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// of all patterns a dag can potentially map to.
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int64_t RawComplexity = R->getValueAsInt("Complexity");
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if (RawComplexity == -1)
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Complexity = NumOperands * 3;
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else
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Complexity = RawComplexity;
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// FIXME: Why is this different from parseSDPatternOperatorProperties?
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// Parse the properties.
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Properties = 0;
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for (const Record *Prop : R->getValueAsListOfDefs("Properties")) {
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if (Prop->getName() == "SDNPHasChain") {
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Properties |= 1 << SDNPHasChain;
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} else if (Prop->getName() == "SDNPOptInGlue") {
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Properties |= 1 << SDNPOptInGlue;
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} else if (Prop->getName() == "SDNPMayStore") {
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Properties |= 1 << SDNPMayStore;
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} else if (Prop->getName() == "SDNPMayLoad") {
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Properties |= 1 << SDNPMayLoad;
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} else if (Prop->getName() == "SDNPSideEffect") {
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Properties |= 1 << SDNPSideEffect;
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} else if (Prop->getName() == "SDNPMemOperand") {
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Properties |= 1 << SDNPMemOperand;
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} else if (Prop->getName() == "SDNPVariadic") {
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Properties |= 1 << SDNPVariadic;
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} else {
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PrintFatalError(R->getLoc(),
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"Unsupported SD Node property '" + Prop->getName() +
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"' on ComplexPattern '" + R->getName() + "'!");
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}
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}
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WantsRoot = R->getValueAsBit("WantsRoot");
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WantsParent = R->getValueAsBit("WantsParent");
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}
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