Kai Luo c0da8a4e40 [CGP][PowerPC] Pre-commit test case for D113872. NFC.

2021-11-16 09:18:49 +00:00

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AArch64

[STATEPOINT] Force implicit-def for lr register.

2021-11-16 12:52:00 +07:00

AMDGPU

AMDGPU: Mark prolog/epilog SCC defs as dead

2021-11-15 21:35:06 -05:00

ARC

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ARM

[ARM] implement support for TLS register based stack protector

2021-11-09 18:19:47 +01:00

AVR

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BPF

BPF: change btf_type_tag BTF output format

2021-11-09 11:34:25 -08:00

CSKY

[CSKY] First patch to construct codegen infra and generate first add instruction

2021-11-01 10:06:56 +08:00

Generic

[asm] Correctly handle special names in variants

2021-11-15 15:37:09 -05:00

Hexagon

[LiveIntervals] Update subranges in processTiedPairs

2021-11-11 12:24:59 +00:00

Inputs

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Lanai

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M68k

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Mips

[SelectionDAG] Optimize expansion for rotates/funnel shifts

2021-11-02 11:38:25 +00:00

MIR

[X86] Update RET/LRET instruction to use the same naming convention as IRET (PR36876). NFC

2021-11-07 15:06:54 +00:00

MSP430

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NVPTX

[NVPTX] Add imm variants for surface and texture instructions

2021-11-10 19:05:03 +03:00

PowerPC

[CGP][PowerPC] Pre-commit test case for D113872. NFC.

2021-11-16 09:18:49 +00:00

RISCV

[RISCV] Override TargetLowering::hasAndNot for Zbb.

2021-11-15 18:44:07 -08:00

SPARC

[SPARC] Zero-extend the operands when doing UMULO on 64-bit integers

2021-11-14 19:59:52 +01:00

SystemZ

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Thumb

[TwoAddressInstructionPass] Update existing physreg live intervals

2021-11-05 21:20:30 +00:00

Thumb2

[ARM] Fix GatherScatter AddLikeOr condition

2021-11-15 09:44:41 +00:00

VE

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WebAssembly

[WebAssembly] Add prototype relaxed float to int trunc instructions

2021-10-28 14:01:53 -07:00

WinCFGuard

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WinEH

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X86

[X86] Fix crash with inline asm using wrong register name

2021-11-16 10:38:12 +08:00

XCore

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