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llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel
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Jay Foad b72f1448ce AMDGPU/GlobalISel: Better code for one case of G_SHUFFLE_VECTOR on v2i16 
Reviewers: arsenm

Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, rovka, dstuttard, tpr, t-tye, hiraditya, kerbowa, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D74987
2020-02-21 21:16:39 +00:00
..
amdgpu-irtranslator.ll
AMDGPU/GlobalISel: Remove unnecesssary REQUIREs
2019-05-29 13:14:35 +00:00
artifact-combiner-anyext.mir
GlobalISel: Fix artifact combiner constant legality checks for vectors
2019-02-07 18:58:28 +00:00
artifact-combiner-extract.mir
GlobalISel: Partially implement lower for G_EXTRACT
2019-10-06 01:37:35 +00:00
artifact-combiner-sext.mir
AMDGPU/GlobalISel: Don't use legal v2s16 G_BUILD_VECTOR
2020-02-05 11:52:18 -05:00
artifact-combiner-unmerge-values.mir
AMDGPU/GlobalISel: Legalize G_SEXT_INREG
2020-02-04 13:23:53 -08:00
artifact-combiner-zext.mir
AMDGPU/GlobalISel: Don't use legal v2s16 G_BUILD_VECTOR
2020-02-05 11:52:18 -05:00
bool-legalization.ll
AMDGPU/GlobalISel: Initial selection of MUBUF addr64 load/store
2020-01-27 07:13:56 -08:00
bswap.ll
AMDGPU/GlobalISel: Improve 16-bit bswap
2020-02-14 15:57:39 -08:00
combine-ashr-narrow.mir
GlobalISel: Fix narrowing of (G_ASHR i64:x, 32)
2020-02-21 16:51:03 +00:00
combine-ext-legalizer.mir
AMDGPU/GlobalISel: Legalize G_SEXT_INREG
2020-02-04 13:23:53 -08:00
combine-lshr-narrow.mir
GlobalISel: Add combine to narrow G_LSHR
2020-02-17 08:04:52 -08:00
combine-shl-narrow.mir
GlobalISel: Extend shift narrowing to G_SHL
2020-02-17 09:13:37 -08:00
constant-bus-restriction.ll
AMDGPU/GlobalISel: Fix constant bus violation with source modifiers
2020-02-21 10:30:23 -05:00
divergent-control-flow.ll
AMDGPU/GlobalISel: Adjust branch target when lowering loop intrinsic
2020-02-18 06:35:40 -08:00
extractelement.ll
AMDGPU/GlobalISel: Fix tablegen selection for scalar bin ops
2020-01-29 08:55:54 -08:00
floor.f64.ll
AMDGPU/GlobalISel: Legalize f64 G_FFLOOR for SI
2020-02-05 14:32:01 -05:00
fmax_legacy.ll
AMDGPU/GlobalISel: Combine FMIN_LEGACY/FMAX_LEGACY
2020-01-31 06:58:04 -08:00
fmin_legacy.ll
AMDGPU/GlobalISel: Combine FMIN_LEGACY/FMAX_LEGACY
2020-01-31 06:58:04 -08:00
fmul.v2f16.ll
AMDGPU/GlobalISel: Select VOP3P instructions
2020-02-21 13:35:40 -05:00
fpow.ll
AMDGPU/GlobalISel: Legalize G_FPOW
2020-02-21 10:31:13 -05:00
function-returns.ll
GlobalISel: Allow CSE of G_IMPLICIT_DEF
2020-02-05 17:47:21 -05:00
global-value.illegal.ll
AMDGPU/GlobalISel: Allow arbitrary global values
2020-02-17 11:32:28 -08:00
global-value.ll
AMDGPU/GlobalISel: Allow arbitrary global values
2020-02-17 11:32:28 -08:00
insertelement.ll
Revert "Revert "Reland "[Support] make report_fatal_error abort instead of exit"""
2020-02-13 10:16:06 -08:00
inst-select-abs.mir
AMDGPU/GlobalISel: Fix import of s_abs_i32 pattern
2020-01-07 10:32:07 -05:00
inst-select-add.mir
AMDGPU/GlobalISel: Fix tablegen selection for scalar bin ops
2020-01-29 08:55:54 -08:00
inst-select-add.s16.mir
AMDGPU/GlobalISel: Fix import of zext of s16 op patterns
2020-01-09 10:29:32 -05:00
inst-select-amdgcn.class.mir
AMDGPU/GlobalISel: Don't use XEXEC class for SGPRs
2020-01-12 22:44:51 -05:00
inst-select-amdgcn.class.s16.mir
AMDGPU: Relax 32-bit SGPR register class
2019-10-18 18:26:37 +00:00
inst-select-amdgcn.cos.mir
AMDGPU: Relax 32-bit SGPR register class
2019-10-18 18:26:37 +00:00
inst-select-amdgcn.cos.s16.mir
AMDGPU: Relax 32-bit SGPR register class
2019-10-18 18:26:37 +00:00
inst-select-amdgcn.cvt.pk.i16.mir
AMDGPU: Relax 32-bit SGPR register class
2019-10-18 18:26:37 +00:00
inst-select-amdgcn.cvt.pk.u16.mir
AMDGPU: Relax 32-bit SGPR register class
2019-10-18 18:26:37 +00:00
inst-select-amdgcn.cvt.pknorm.i16.mir
AMDGPU: Relax 32-bit SGPR register class
2019-10-18 18:26:37 +00:00
inst-select-amdgcn.cvt.pknorm.u16.mir
AMDGPU: Relax 32-bit SGPR register class
2019-10-18 18:26:37 +00:00
inst-select-amdgcn.cvt.pkrtz.mir
AMDGPU: Relax 32-bit SGPR register class
2019-10-18 18:26:37 +00:00
inst-select-amdgcn.ds.swizzle.mir
TableGen/GlobalISel: Add way for SDNodeXForm to work on timm
2020-01-09 17:37:52 -05:00
inst-select-amdgcn.exp.mir
AMDGPU/GlobalISel: Select exp with patterns
2020-01-15 18:33:15 -05:00
inst-select-amdgcn.fmad.ftz.mir
AMDGPU/GlobalISel: Select llvm.amdgcn.fmad.ftz
2019-12-30 11:12:35 -05:00
inst-select-amdgcn.fmed3.mir
AMDGPU: Relax 32-bit SGPR register class
2019-10-18 18:26:37 +00:00
inst-select-amdgcn.fmed3.s16.mir
AMDGPU: Relax 32-bit SGPR register class
2019-10-18 18:26:37 +00:00
inst-select-amdgcn.fract.mir
AMDGPU/GlobalISel: Don't use XEXEC class for SGPRs
2020-01-12 22:44:51 -05:00
inst-select-amdgcn.fract.s16.mir
AMDGPU: Relax 32-bit SGPR register class
2019-10-18 18:26:37 +00:00
inst-select-amdgcn.ldexp.mir
AMDGPU/GlobalISel: Don't use XEXEC class for SGPRs
2020-01-12 22:44:51 -05:00
inst-select-amdgcn.ldexp.s16.mir
AMDGPU: Relax 32-bit SGPR register class
2019-10-18 18:26:37 +00:00
inst-select-amdgcn.mbcnt.lo.mir
AMDGPU: Relax 32-bit SGPR register class
2019-10-18 18:26:37 +00:00
inst-select-amdgcn.mul.u24.mir
AMDGPU/GlobalISel: Select mul24 intrinsics
2019-12-30 14:24:25 -05:00
inst-select-amdgcn.rcp.legacy.mir
AMDGPU: Relax 32-bit SGPR register class
2019-10-18 18:26:37 +00:00
inst-select-amdgcn.rcp.mir
AMDGPU/GlobalISel: Don't use XEXEC class for SGPRs
2020-01-12 22:44:51 -05:00
inst-select-amdgcn.rcp.s16.mir
AMDGPU: Relax 32-bit SGPR register class
2019-10-18 18:26:37 +00:00
inst-select-amdgcn.readfirstlane.mir
AMDGPU/GlobalISel: Fix readfirstlane pattern import
2020-01-07 11:07:08 -05:00
inst-select-amdgcn.rsq.clamp.mir
AMDGPU: Relax 32-bit SGPR register class
2019-10-18 18:26:37 +00:00
inst-select-amdgcn.rsq.legacy.mir
AMDGPU: Relax 32-bit SGPR register class
2019-10-18 18:26:37 +00:00
inst-select-amdgcn.rsq.mir
AMDGPU/GlobalISel: Don't use XEXEC class for SGPRs
2020-01-12 22:44:51 -05:00
inst-select-amdgcn.rsq.s16.mir
AMDGPU: Relax 32-bit SGPR register class
2019-10-18 18:26:37 +00:00
inst-select-amdgcn.s.barrier.mir
AMDGPU/GlobalISel: Try generated matcher with intrinsics
2019-07-02 14:52:16 +00:00
inst-select-amdgcn.s.sendmsg.mir
AMDGPU: Relax 32-bit SGPR register class
2019-10-18 18:26:37 +00:00
inst-select-amdgcn.sffbh.mir
AMDGPU: Relax 32-bit SGPR register class
2019-10-18 18:26:37 +00:00
inst-select-amdgcn.sin.mir
AMDGPU: Relax 32-bit SGPR register class
2019-10-18 18:26:37 +00:00
inst-select-amdgcn.sin.s16.mir
AMDGPU: Relax 32-bit SGPR register class
2019-10-18 18:26:37 +00:00
inst-select-amdgpu-atomic-cmpxchg-flat.mir
[globalisel] Rename G_GEP to G_PTR_ADD
2019-11-05 10:31:17 -08:00
inst-select-amdgpu-atomic-cmpxchg-global.mir
AMDGPU/GlobalISel: Select MUBUF path for global atomic cmpxchg
2020-02-19 06:19:22 -08:00
inst-select-amdgpu-ffbh-u32.mir
AMDGPU: Relax 32-bit SGPR register class
2019-10-18 18:26:37 +00:00
inst-select-and.mir
AMDGPU/GlobalISel: Fix xnor matching
2020-02-21 11:42:49 -05:00
inst-select-anyext.mir
AMDGPU/GlobalISel: Remove extension legality hacks
2020-02-04 12:50:47 -08:00
inst-select-ashr.mir
[AMDGPU] fixed divergence driven shift operations selection
2020-01-31 20:49:56 +03:00
inst-select-ashr.s16.mir
AMDGPU/GlobalISel: Fix import of zext of s16 op patterns
2020-01-09 10:29:32 -05:00
inst-select-ashr.v2s16.mir
AMDGPU/GlobalISel: Select VOP3P instructions
2020-02-21 13:35:40 -05:00
inst-select-atomic-cmpxchg-local.mir
AMDGPU/GlobalISel: Add missing tests for cmpxchg selection
2020-02-13 10:26:55 -08:00
inst-select-atomicrmw-add-flat.mir
AMDGPU/GlobalISel: Add selection tests for G_ATOMICRMW_ADD
2020-01-24 12:15:09 -08:00
inst-select-atomicrmw-add-global.mir
AMDGPU/GlobalISel: Select global MUBUF atomicrmw
2020-01-31 06:05:41 -08:00
inst-select-atomicrmw-fadd-local.mir
[globalisel] Rename G_GEP to G_PTR_ADD
2019-11-05 10:31:17 -08:00
inst-select-atomicrmw-xchg-local.mir
[globalisel] Rename G_GEP to G_PTR_ADD
2019-11-05 10:31:17 -08:00
inst-select-bitcast.mir
AMDGPU/GlobalISel: Prepare some tests for store selection
2019-07-09 14:30:57 +00:00
inst-select-bitreverse.mir
AMDGPU: Relax 32-bit SGPR register class
2019-10-18 18:26:37 +00:00
inst-select-br.mir
AMDGPU/GlobalISel: Select G_BRCOND for scc conditions
2019-07-01 15:39:27 +00:00
inst-select-brcond.mir
AMDGPU/GlobalISel: Replace handling of boolean values
2020-01-06 18:26:42 -05:00
inst-select-bswap.mir
AMDGPU/GlobalISel: Handle G_BSWAP
2020-02-14 09:09:44 -08:00
inst-select-build-vector-trunc.v2s16.mir
AMDGPU/GlobalISel: Commit test changes I forgot to squash
2020-02-21 11:43:39 -05:00
inst-select-build-vector.mir
AMDGPU/GlobalISel: Don't use XEXEC class for SGPRs
2020-01-12 22:44:51 -05:00
inst-select-concat-vectors.mir
[AMDGPU][GlobalISel] Handle 64byte EltSIze in getRegSplitParts
2020-02-12 19:11:52 -08:00
inst-select-constant.mir
AMDGPU/GlobalISel: Don't use XEXEC class for SGPRs
2020-01-12 22:44:51 -05:00
inst-select-copy.mir
AMDGPU/GlobalISel: Initial selection of MUBUF addr64 load/store
2020-01-27 07:13:56 -08:00
inst-select-ctlz-zero-undef.mir
AMDGPU/GlobalISel: Select G_CTLZ_ZERO_UNDEF
2020-02-12 16:19:45 -08:00
inst-select-ctpop.mir
AMDGPU/GlobalISel: Fix missing test for select of s64 scalar G_CTPOP
2020-02-07 13:15:48 -05:00
inst-select-cttz-zero-undef.mir
AMDGPU/GlobalISel: Select G_CTTZ_ZERO_UNDEF
2020-02-12 16:19:46 -08:00
inst-select-extract-vector-elt.mir
AMDGPU/GlobalISel: Don't mis-select vector index on a constant
2020-02-09 18:02:37 -05:00
inst-select-extract.mir
AMDGPU/GlobalISel: Fix G_EXTRACT of 96-bit results
2020-02-14 15:57:40 -08:00
inst-select-fabs.mir
AMDGPU/GlobalISel: Don't use XEXEC class for SGPRs
2020-01-12 22:44:51 -05:00
inst-select-fadd.s16.mir
AMDGPU/GlobalISel: Rewrite fadd select tests
2020-01-29 07:49:38 -08:00
inst-select-fadd.s32.mir
AMDGPU/GlobalISel: Fix constant bus violation with source modifiers
2020-02-21 10:30:23 -05:00
inst-select-fadd.s64.mir
AMDGPU/GlobalISel: Fix constant bus violation with source modifiers
2020-02-21 10:30:23 -05:00
inst-select-fcanonicalize.mir
AMDGPU/GlobalISel: Select VOP3P instructions
2020-02-21 13:35:40 -05:00
inst-select-fceil.mir
AMDGPU/GlobalISel: Don't use XEXEC class for SGPRs
2020-01-12 22:44:51 -05:00
inst-select-fceil.s16.mir
AMDGPU/GlobalISel: Legalize some 16-bit round instructions
2019-12-24 09:53:01 -05:00
inst-select-fcmp.mir
AMDGPU/GlobalISel: Replace handling of boolean values
2020-01-06 18:26:42 -05:00
inst-select-fcmp.s16.mir
AMDGPU: Relax 32-bit SGPR register class
2019-10-18 18:26:37 +00:00
inst-select-fexp2.mir
AMDGPU/GlobalISel: Add select test for fexp2
2019-12-30 10:56:37 -05:00
inst-select-ffloor.s16.mir
AMDGPU: Relax 32-bit SGPR register class
2019-10-18 18:26:37 +00:00
inst-select-ffloor.s32.mir
AMDGPU/GlobalISel: Legalize f64 G_FFLOOR for SI
2020-02-05 14:32:01 -05:00
inst-select-ffloor.s64.mir
AMDGPU/GlobalISel: Legalize f64 G_FFLOOR for SI
2020-02-05 14:32:01 -05:00
inst-select-fma.s32.mir
AMDGPU/GlobalISel: Look through copies for source modifiers
2020-01-29 08:08:13 -08:00
inst-select-fmad.s32.mir
AMDGPU/GlobalISel: Look through copies for source modifiers
2020-01-29 08:08:13 -08:00
inst-select-fmaxnum-ieee.mir
AMDGPU/GlobalISel: Initial selection of MUBUF addr64 load/store
2020-01-27 07:13:56 -08:00
inst-select-fmaxnum-ieee.s16.mir
AMDGPU/GlobalISel: Fix tests without asserts
2019-07-22 12:43:41 +00:00
inst-select-fmaxnum-ieee.v2s16.mir
AMDGPU/GlobalISel: Select VOP3P instructions
2020-02-21 13:35:40 -05:00
inst-select-fmaxnum.mir
AMDGPU/GlobalISel: Initial selection of MUBUF addr64 load/store
2020-01-27 07:13:56 -08:00
inst-select-fmaxnum.s16.mir
AMDGPU/GlobalISel: Fix tests without asserts
2019-07-22 12:43:41 +00:00
inst-select-fmaxnum.v2s16.mir
AMDGPU/GlobalISel: Select VOP3P instructions
2020-02-21 13:35:40 -05:00
inst-select-fminnum-ieee.mir
AMDGPU/GlobalISel: Initial selection of MUBUF addr64 load/store
2020-01-27 07:13:56 -08:00
inst-select-fminnum-ieee.s16.mir
AMDGPU/GlobalISel: Fix tests without asserts
2019-07-22 12:43:41 +00:00
inst-select-fminnum-ieee.v2s16.mir
AMDGPU/GlobalISel: Select VOP3P instructions
2020-02-21 13:35:40 -05:00
inst-select-fminnum.mir
AMDGPU/GlobalISel: Initial selection of MUBUF addr64 load/store
2020-01-27 07:13:56 -08:00
inst-select-fminnum.s16.mir
AMDGPU/GlobalISel: Fix tests without asserts
2019-07-22 12:43:41 +00:00
inst-select-fminnum.v2s16.mir
AMDGPU/GlobalISel: Select VOP3P instructions
2020-02-21 13:35:40 -05:00
inst-select-fmul.mir
AMDGPU/GlobalISel: Don't use XEXEC class for SGPRs
2020-01-12 22:44:51 -05:00
inst-select-fmul.v2s16.mir
AMDGPU/GlobalISel: Select VOP3P instructions
2020-02-21 13:35:40 -05:00
inst-select-fneg.mir
AMDGPU/GlobalISel: Manually select scalar f64 G_FNEG
2020-01-29 06:49:16 -08:00
inst-select-fptosi.mir
AMDGPU: Relax 32-bit SGPR register class
2019-10-18 18:26:37 +00:00
inst-select-fptoui.mir
AMDGPU/GlobalISel: Initial selection of MUBUF addr64 load/store
2020-01-27 07:13:56 -08:00
inst-select-frame-index.mir
AMDGPU: Relax 32-bit SGPR register class
2019-10-18 18:26:37 +00:00
inst-select-frint.s16.mir
AMDGPU/GlobalISel: Legalize some 16-bit round instructions
2019-12-24 09:53:01 -05:00
inst-select-icmp.mir
AMDGPU/GlobalISel: Replace handling of boolean values
2020-01-06 18:26:42 -05:00
inst-select-icmp.s16.mir
AMDGPU/GlobalISel: Fix missing test for s16 icmp
2020-01-07 16:36:31 -05:00
inst-select-icmp.s64.mir
AMDGPU/GlobalISel: Replace handling of boolean values
2020-01-06 18:26:42 -05:00
inst-select-implicit-def.mir
AMDGPU/GlobalISel: Initial selection of MUBUF addr64 load/store
2020-01-27 07:13:56 -08:00
inst-select-insert-vector-elt.mir
AMDGPU/GlobalISel: Don't mis-select vector index on a constant
2020-02-09 18:02:37 -05:00
inst-select-insert.mir
AMDGPU/GlobalISel: Don't use XEXEC class for SGPRs
2020-01-12 22:44:51 -05:00
inst-select-intrinsic-trunc.mir
AMDGPU/GlobalISel: Don't use XEXEC class for SGPRs
2020-01-12 22:44:51 -05:00
inst-select-intrinsic-trunc.s16.mir
AMDGPU/GlobalISel: Legalize some 16-bit round instructions
2019-12-24 09:53:01 -05:00
inst-select-inttoptr.mir
AMDGPU/GlobalISel: Initial selection of MUBUF addr64 load/store
2020-01-27 07:13:56 -08:00
inst-select-load-atomic-flat.mir
[globalisel] Rename G_GEP to G_PTR_ADD
2019-11-05 10:31:17 -08:00
inst-select-load-atomic-global.mir
AMDPGPU/GlobalISel: Select more MUBUF global addressing modes
2020-01-27 07:28:36 -08:00
inst-select-load-atomic-local.mir
[globalisel] Rename G_GEP to G_PTR_ADD
2019-11-05 10:31:17 -08:00
inst-select-load-constant.mir
Reapply "AMDGPU: Cleanup and fix SMRD offset handling"
2020-01-31 06:01:28 -08:00
inst-select-load-flat.mir
AMDGPU/GlobalISel: Allow selecting s128 load/stores
2020-02-03 12:28:08 -08:00
inst-select-load-global.mir
AMDGPU/GlobalISel: Allow selecting s128 load/stores
2020-02-03 12:28:08 -08:00
inst-select-load-global.s96.mir
AMDGPU/GlobalISel: Fix tests in release build
2020-01-29 12:27:16 -08:00
inst-select-load-local-128.mir
AMDGPU/GlobalISel: First pass at attempting to legalize load/stores
2019-09-10 16:20:14 +00:00
inst-select-load-local.mir
[AMDGPU][GlobalISel] Select 8-byte LDS Ops with 4-byte alignment
2020-01-29 10:42:12 -08:00
inst-select-load-private.mir
[globalisel] Rename G_GEP to G_PTR_ADD
2019-11-05 10:31:17 -08:00
inst-select-load-smrd.mir
AMDGPU/GlobalISel: Don't use XEXEC class for SGPRs
2020-01-12 22:44:51 -05:00
inst-select-lshr.mir
[AMDGPU] fixed divergence driven shift operations selection
2020-01-31 20:49:56 +03:00
inst-select-lshr.s16.mir
AMDGPU/GlobalISel: Fix import of zext of s16 op patterns
2020-01-09 10:29:32 -05:00
inst-select-lshr.v2s16.mir
AMDGPU/GlobalISel: Select VOP3P instructions
2020-02-21 13:35:40 -05:00
inst-select-merge-values.mir
AMDGPU/GlobalISel: Don't use XEXEC class for SGPRs
2020-01-12 22:44:51 -05:00
inst-select-mul.mir
AMDGPU: Relax 32-bit SGPR register class
2019-10-18 18:26:37 +00:00
inst-select-or.mir
AMDGPU/GlobalISel: Fix xnor matching
2020-02-21 11:42:49 -05:00
inst-select-pattern-add3.mir
AMDGPU/GlobalISel: Fix tablegen selection for scalar bin ops
2020-01-29 08:55:54 -08:00
inst-select-pattern-or3.mir
AMDGPU/GlobalISel: Fix xnor matching
2020-02-21 11:42:49 -05:00
inst-select-pattern-smed3.mir
AMDGPU/GlobalISel: Fix import of integer med3
2020-01-09 10:29:32 -05:00
inst-select-pattern-smed3.s16.mir
AMDGPU/GlobalISel: Fix import of integer med3
2020-01-09 10:29:32 -05:00
inst-select-pattern-umed3.mir
AMDGPU/GlobalISel: Fix import of integer med3
2020-01-09 10:29:32 -05:00
inst-select-pattern-umed3.s16.mir
AMDGPU/GlobalISel: Fix import of integer med3
2020-01-09 10:29:32 -05:00
inst-select-pattern-xor3.mir
AMDGPU/GlobalISel: Fix xnor matching
2020-02-21 11:42:49 -05:00
inst-select-pattern-xor3.xfail.mir
Revert "Revert "Reland "[Support] make report_fatal_error abort instead of exit"""
2020-02-13 10:16:06 -08:00
inst-select-phi.mir
AMDGPU/GlobalISel: Don't use XEXEC class for SGPRs
2020-01-12 22:44:51 -05:00
inst-select-ptr-add.mir
AMDGPU/GlobalISel: Legalize G_PTR_ADD for arbitrary pointers
2020-01-21 16:35:36 -05:00
inst-select-ptr-mask.mir
AMDGPU/GlobalISel: Don't use XEXEC class for SGPRs
2020-01-12 22:44:51 -05:00
inst-select-ptrtoint.mir
AMDGPU/GlobalISel: Don't use XEXEC class for SGPRs
2020-01-12 22:44:51 -05:00
inst-select-select.mir
AMDGPU/GlobalISel: Eliminate SelectVOP3Mods_f32
2020-01-27 17:53:54 -05:00
inst-select-sext-inreg.mir
AMDGPU/GlobalISel: Select G_SEXT_INREG
2020-02-04 13:23:53 -08:00
inst-select-sext.mir
AMDGPU/GlobalISel: Remove extension legality hacks
2020-02-04 12:50:47 -08:00
inst-select-shl.mir
[AMDGPU] fixed divergence driven shift operations selection
2020-01-31 20:49:56 +03:00
inst-select-shl.s16.mir
AMDGPU/GlobalISel: Fix import of zext of s16 op patterns
2020-01-09 10:29:32 -05:00
inst-select-shl.v2s16.mir
AMDGPU/GlobalISel: Select VOP3P instructions
2020-02-21 13:35:40 -05:00
inst-select-shuffle-vector.v2s16.mir
AMDGPU/GlobalISel: Better code for one case of G_SHUFFLE_VECTOR on v2i16
2020-02-21 21:16:39 +00:00
inst-select-sitofp.mir
AMDGPU/GlobalISel: Initial selection of MUBUF addr64 load/store
2020-01-27 07:13:56 -08:00
inst-select-smax.mir
AMDGPU: Relax 32-bit SGPR register class
2019-10-18 18:26:37 +00:00
inst-select-smin.mir
AMDGPU: Relax 32-bit SGPR register class
2019-10-18 18:26:37 +00:00
inst-select-smulh.mir
AMDGPU/GlobalISel: Fix tablegen selection for scalar bin ops
2020-01-29 08:55:54 -08:00
inst-select-store-flat.mir
AMDGPU/GlobalISel: Allow selecting s128 load/stores
2020-02-03 12:28:08 -08:00
inst-select-store-global.mir
AMDGPU/GlobalISel: Split 96-bit load/store select tests out
2020-02-12 09:58:37 -05:00
inst-select-store-global.s96.mir
AMDGPU/GlobalISel: Split 96-bit load/store select tests out
2020-02-12 09:58:37 -05:00
inst-select-store-local.mir
[AMDGPU][GlobalISel] Select 8-byte LDS Ops with 4-byte alignment
2020-01-29 10:42:12 -08:00
inst-select-store-private.mir
[globalisel] Rename G_GEP to G_PTR_ADD
2019-11-05 10:31:17 -08:00
inst-select-sub.mir
AMDGPU/GlobalISel: Fix tablegen selection for scalar bin ops
2020-01-29 08:55:54 -08:00
inst-select-trunc.mir
AMDGPU/GlobalISel: Don't use XEXEC class for SGPRs
2020-01-12 22:44:51 -05:00
inst-select-trunc.v2s16.mir
AMDGPU/GlobalISel: Select v2s32->v2s16 G_TRUNC
2020-02-17 09:20:13 -05:00
inst-select-uadde.gfx10.mir
AMDGPU/GlobalISel: Select G_UADDE/G_USUBE
2020-01-06 18:27:52 -05:00
inst-select-uadde.mir
AMDGPU/GlobalISel: Select G_UADDE/G_USUBE
2020-01-06 18:27:52 -05:00
inst-select-uaddo.mir
AMDGPU/GlobalISel: Replace handling of boolean values
2020-01-06 18:26:42 -05:00
inst-select-uitofp.mir
GlobalISel: Lower s1 source G_SITOFP/G_UITOFP
2019-11-15 13:37:20 +05:30
inst-select-umax.mir
AMDGPU: Relax 32-bit SGPR register class
2019-10-18 18:26:37 +00:00
inst-select-umin.mir
AMDGPU: Relax 32-bit SGPR register class
2019-10-18 18:26:37 +00:00
inst-select-umulh.mir
AMDGPU/GlobalISel: Fix tablegen selection for scalar bin ops
2020-01-29 08:55:54 -08:00
inst-select-unmerge-values.mir
AMDGPU/GlobalISel: Don't use XEXEC class for SGPRs
2020-01-12 22:44:51 -05:00
inst-select-usube.gfx10.mir
AMDGPU/GlobalISel: Select G_UADDE/G_USUBE
2020-01-06 18:27:52 -05:00
inst-select-usube.mir
AMDGPU/GlobalISel: Select G_UADDE/G_USUBE
2020-01-06 18:27:52 -05:00
inst-select-usubo.mir
AMDGPU/GlobalISel: Replace handling of boolean values
2020-01-06 18:26:42 -05:00
inst-select-xor.mir
AMDGPU/GlobalISel: Fix xnor matching
2020-02-21 11:42:49 -05:00
inst-select-zext.mir
AMDGPU/GlobalISel: Remove extension legality hacks
2020-02-04 12:50:47 -08:00
irtranslator-amdgcn-sendmsg.ll
Reapply r372285 "GlobalISel: Don't materialize immarg arguments to intrinsics"
2019-09-19 16:26:14 +00:00
irtranslator-amdgpu_kernel-system-sgprs.ll
AMDGPU/GlobalISel: Legalize workgroup ID intrinsics
2019-07-01 18:47:22 +00:00
irtranslator-amdgpu_kernel.ll
[AMDGPU] Don't create MachinePointerInfos with an UndefValue pointer
2019-12-23 15:58:19 +00:00
irtranslator-amdgpu_ps.ll
GlobalISel: Allow CSE of G_IMPLICIT_DEF
2020-02-05 17:47:21 -05:00
irtranslator-amdgpu_vs.ll
Reapply r372285 "GlobalISel: Don't materialize immarg arguments to intrinsics"
2019-09-19 16:26:14 +00:00
irtranslator-atomicrmw.ll
GlobalISel: Add G_ATOMICRMW_{FADD|FSUB}
2019-07-30 23:56:30 +00:00
irtranslator-fast-math-flags.ll
AMDGPU/GlobalISel: Legalize workitem ID intrinsics
2019-07-01 18:45:36 +00:00
irtranslator-fence.ll
GlobalISel: Add G_FENCE
2019-07-02 14:16:39 +00:00
irtranslator-function-args.ll
GlobalISel: Allow CSE of G_IMPLICIT_DEF
2020-02-05 17:47:21 -05:00
irtranslator-getelementptr.ll
[GlobalISel][IRTranslator] Follow convention and put constant offset of getelementptr arithmetic on RHS.
2020-01-29 11:37:19 -08:00
irtranslator-readnone-intrinsic-callsite.ll
GlobalISel: Ignore callsite attributes when picking intrinsic type
2019-06-17 17:01:35 +00:00
irtranslator-struct-return-intrinsics.ll
GlobalISel: Allow CSE of G_IMPLICIT_DEF
2020-02-05 17:47:21 -05:00
lds-global-non-entry-func.ll
AMDGPU/GlobalISel: Implement LDS G_GLOBAL_VALUE
2019-09-09 17:13:44 +00:00
lds-global-value.ll
AMDGPU/GlobalISel: Implement LDS G_GLOBAL_VALUE
2019-09-09 17:13:44 +00:00
lds-relocs.ll
[GlobalISel] Add new combine to convert scalar G_MUL to G_SHL.
2020-01-29 13:39:00 -08:00
lds-size.ll
AMDGPU/GlobalISel: Implement LDS G_GLOBAL_VALUE
2019-09-09 17:13:44 +00:00
lds-zero-initializer.ll
Revert "Revert "Reland "[Support] make report_fatal_error abort instead of exit"""
2020-02-13 10:16:06 -08:00
legalize-add.mir
AMDGPU/GlobalISel: Fix non-pow-2 add/sub/mul for 16-bit insts
2020-02-06 21:43:54 -05:00
legalize-addrspacecast.mir
[AMDGPU] Don't create MachinePointerInfos with an UndefValue pointer
2019-12-23 15:58:19 +00:00
legalize-amdgcn.if-invalid.mir
AMDGPU/GlobalISel: Custom lower control flow intrinsics
2019-07-01 18:40:23 +00:00
legalize-amdgcn.wavefrontsize.mir
AMDGPU/GlobalISel: Legalize wavefrontsize intrinsic
2019-09-09 15:20:49 +00:00
legalize-and.mir
GlobalISel: Allow CSE of G_IMPLICIT_DEF
2020-02-05 17:47:21 -05:00
legalize-anyext.mir
AMDGPU/GlobalISel: Remove extension legality hacks
2020-02-04 12:50:47 -08:00
legalize-ashr.mir
GlobalISel: Allow CSE of G_IMPLICIT_DEF
2020-02-05 17:47:21 -05:00
legalize-atomic-cmpxchg-with-success.mir
AMDGPU/GlobalISel: Handle flat/global G_ATOMIC_CMPXCHG
2019-10-25 13:11:09 -07:00
legalize-atomic-cmpxchg.mir
AMDGPU/GlobalISel: Handle flat/global G_ATOMIC_CMPXCHG
2019-10-25 13:11:09 -07:00
legalize-atomicrmw-add.mir
AMDGPU/GlobalISel: Legality/regbankselect for atomicrmw/atomic_cmpxchg
2018-12-20 00:33:49 +00:00
legalize-atomicrmw-and.mir
AMDGPU/GlobalISel: Legality/regbankselect for atomicrmw/atomic_cmpxchg
2018-12-20 00:33:49 +00:00
legalize-atomicrmw-fadd.mir
AMDGPU/GlobalISel: Handle G_ATOMICRMW_FADD
2019-08-01 03:33:15 +00:00
legalize-atomicrmw-max.mir
AMDGPU/GlobalISel: Legality/regbankselect for atomicrmw/atomic_cmpxchg
2018-12-20 00:33:49 +00:00
legalize-atomicrmw-min.mir
AMDGPU/GlobalISel: Legality/regbankselect for atomicrmw/atomic_cmpxchg
2018-12-20 00:33:49 +00:00
legalize-atomicrmw-nand.mir
Revert "Revert "Reland "[Support] make report_fatal_error abort instead of exit"""
2020-02-13 10:16:06 -08:00
legalize-atomicrmw-or.mir
AMDGPU/GlobalISel: Legality/regbankselect for atomicrmw/atomic_cmpxchg
2018-12-20 00:33:49 +00:00
legalize-atomicrmw-sub.mir
AMDGPU/GlobalISel: Legality/regbankselect for atomicrmw/atomic_cmpxchg
2018-12-20 00:33:49 +00:00
legalize-atomicrmw-umax.mir
AMDGPU/GlobalISel: Legality/regbankselect for atomicrmw/atomic_cmpxchg
2018-12-20 00:33:49 +00:00
legalize-atomicrmw-umin.mir
AMDGPU/GlobalISel: Legality/regbankselect for atomicrmw/atomic_cmpxchg
2018-12-20 00:33:49 +00:00
legalize-atomicrmw-xchg-flat.mir
Revert "Revert "Reland "[Support] make report_fatal_error abort instead of exit"""
2020-02-13 10:16:06 -08:00
legalize-atomicrmw-xchg.mir
AMDGPU/GlobalISel: Legality/regbankselect for atomicrmw/atomic_cmpxchg
2018-12-20 00:33:49 +00:00
legalize-atomicrmw-xor.mir
AMDGPU/GlobalISel: Legality/regbankselect for atomicrmw/atomic_cmpxchg
2018-12-20 00:33:49 +00:00
legalize-bitcast.mir
AMDGPU/GlobalISel: Remove bitcast legality hack
2020-02-05 16:24:24 -05:00
legalize-bitreverse.mir
AMDGPU/GlobalISel: Don't use legal v2s16 G_BUILD_VECTOR
2020-02-05 11:52:18 -05:00
legalize-block-addr.mir
[Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing
2019-09-11 11:16:48 +00:00
legalize-brcond.mir
AMDGPU/GlobalISel: Replace handling of boolean values
2020-01-06 18:26:42 -05:00
legalize-bswap.mir
AMDGPU/GlobalISel: Improve 16-bit bswap
2020-02-14 15:57:39 -08:00
legalize-build-vector-trunc.mir
AMDGPU/GlobalISel: Legalize G_BUILD_VECTOR_TRUNC
2019-09-09 17:04:18 +00:00
legalize-build-vector.mir
AMDGPU/GlobalISel: Don't use legal v2s16 G_BUILD_VECTOR
2020-02-05 11:52:18 -05:00
legalize-build-vector.s16.mir
AMDGPU/GlobalISel: Don't use legal v2s16 G_BUILD_VECTOR
2020-02-05 11:52:18 -05:00
legalize-concat-vectors.mir
AMDGPU/GlobalISel: Legalize more concat_vectors
2019-07-09 14:17:31 +00:00
legalize-constant.mir
AMDGPU/GlobalISel: Make 16-bit constants legal
2019-09-04 16:19:45 +00:00
legalize-ctlz-zero-undef.mir
AMDGPU/GlobalISel: Don't use legal v2s16 G_BUILD_VECTOR
2020-02-05 11:52:18 -05:00
legalize-ctlz.mir
GlobalISel: Fix lowering of G_CTLZ/G_CTTZ
2020-02-07 06:54:12 -08:00
legalize-ctpop.mir
AMDGPU/GlobalISel: Don't use legal v2s16 G_BUILD_VECTOR
2020-02-05 11:52:18 -05:00
legalize-cttz-zero-undef.mir
AMDGPU/GlobalISel: Don't use legal v2s16 G_BUILD_VECTOR
2020-02-05 11:52:18 -05:00
legalize-cttz.mir
GlobalISel: Fix lowering of G_CTLZ/G_CTTZ
2020-02-07 06:54:12 -08:00
legalize-extract-vector-elt.mir
AMDGPU/GlobalISel: Look through casts when legalizing vector indexing
2020-02-09 18:02:10 -05:00
legalize-extract.mir
GlobalISel: Allow CSE of G_IMPLICIT_DEF
2020-02-05 17:47:21 -05:00
legalize-fabs.mir
GlobalISel: Allow CSE of G_IMPLICIT_DEF
2020-02-05 17:47:21 -05:00
legalize-fadd.mir
GlobalISel: Allow CSE of G_IMPLICIT_DEF
2020-02-05 17:47:21 -05:00
legalize-fcanonicalize.mir
GlobalISel: Allow CSE of G_IMPLICIT_DEF
2020-02-05 17:47:21 -05:00
legalize-fceil.mir
AMDGPU/GlobalISel: Legalize some 16-bit round instructions
2019-12-24 09:53:01 -05:00
legalize-fcmp.mir
AMDGPU/GlobalISel: Don't use legal v2s16 G_BUILD_VECTOR
2020-02-05 11:52:18 -05:00
legalize-fconstant.mir
AMDGPU/GlobalISel: Make 16-bit constants legal
2019-09-04 16:19:45 +00:00
legalize-fcopysign.mir
AMDGPU/GlobalISel: Don't use legal v2s16 G_BUILD_VECTOR
2020-02-05 11:52:18 -05:00
legalize-fcos.mir
GlobalISel: Allow CSE of G_IMPLICIT_DEF
2020-02-05 17:47:21 -05:00
legalize-fdiv.mir
GlobalISel: Allow CSE of G_IMPLICIT_DEF
2020-02-05 17:47:21 -05:00
legalize-fexp2.mir
AMDGPU/GlobalISel: Don't use legal v2s16 G_BUILD_VECTOR
2020-02-05 11:52:18 -05:00
legalize-fexp.mir
AMDGPU/GlobalISel: Don't use legal v2s16 G_BUILD_VECTOR
2020-02-05 11:52:18 -05:00
legalize-ffloor.mir
GlobalISel: Allow CSE of G_IMPLICIT_DEF
2020-02-05 17:47:21 -05:00
legalize-flog2.mir
GlobalISel: fewerElementsVector for a few more trivial ops
2019-01-25 04:03:38 +00:00
legalize-flog10.mir
AMDGPU/GlobalISel: Don't use legal v2s16 G_BUILD_VECTOR
2020-02-05 11:52:18 -05:00
legalize-flog.mir
AMDGPU/GlobalISel: Don't use legal v2s16 G_BUILD_VECTOR
2020-02-05 11:52:18 -05:00
legalize-fma.mir
GlobalISel: Allow CSE of G_IMPLICIT_DEF
2020-02-05 17:47:21 -05:00
legalize-fmad.s16.mir
AMDGPU/GlobalISel: Don't use legal v2s16 G_BUILD_VECTOR
2020-02-05 11:52:18 -05:00
legalize-fmad.s32.mir
AMDGPU: Split denormal mode tracking bits
2020-02-04 10:44:21 -08:00
legalize-fmad.s64.mir
AMDGPU: Split denormal mode tracking bits
2020-02-04 10:44:21 -08:00
legalize-fmaxnum.mir
GlobalISel: Allow CSE of G_IMPLICIT_DEF
2020-02-05 17:47:21 -05:00
legalize-fminnum.mir
GlobalISel: Allow CSE of G_IMPLICIT_DEF
2020-02-05 17:47:21 -05:00
legalize-fmul.mir
GlobalISel: Allow CSE of G_IMPLICIT_DEF
2020-02-05 17:47:21 -05:00
legalize-fneg.mir
GlobalISel: Allow CSE of G_IMPLICIT_DEF
2020-02-05 17:47:21 -05:00
legalize-fpext.mir
GlobalISel: Allow CSE of G_IMPLICIT_DEF
2020-02-05 17:47:21 -05:00
legalize-fpow.mir
AMDGPU/GlobalISel: Legalize G_FPOW
2020-02-21 10:31:13 -05:00
legalize-fptosi.mir
AMDGPU/GlobalISel: Legalize f64 G_FFLOOR for SI
2020-02-05 14:32:01 -05:00
legalize-fptoui.mir
AMDGPU/GlobalISel: Legalize f64 G_FFLOOR for SI
2020-02-05 14:32:01 -05:00
legalize-fptrunc.mir
GlobalISel: Lower s64->s16 G_FPTRUNC
2020-02-14 10:46:58 -08:00
legalize-frint.mir
[GISel] Allow getConstantVRegVal() to return G_FCONSTANT values.
2019-10-10 21:46:26 +00:00
legalize-fsin.mir
GlobalISel: Allow CSE of G_IMPLICIT_DEF
2020-02-05 17:47:21 -05:00
legalize-fsqrt.mir
GlobalISel: Allow CSE of G_IMPLICIT_DEF
2020-02-05 17:47:21 -05:00
legalize-fsub.mir
GlobalISel: Allow CSE of G_IMPLICIT_DEF
2020-02-05 17:47:21 -05:00
legalize-icmp.mir
AMDGPU/GlobalISel: Add some missing tests for non-power-of-2 cases
2020-02-16 22:48:42 -05:00
legalize-implicit-def.mir
AMDGPU/GlobalISel: Increase max legal size to 1024
2019-10-01 16:35:06 +00:00
legalize-insert-vector-elt.mir
AMDGPU/GlobalISel: Look through casts when legalizing vector indexing
2020-02-09 18:02:10 -05:00
legalize-insert.mir
GlobalISel: Allow CSE of G_IMPLICIT_DEF
2020-02-05 17:47:21 -05:00
legalize-intrinsic-amdgcn-fdiv-fast.mir
[update_mir_test_checks] Handle MI flags properly
2019-10-14 22:01:58 +00:00
legalize-intrinsic-round.mir
GlobalISel: Allow CSE of G_IMPLICIT_DEF
2020-02-05 17:47:21 -05:00
legalize-intrinsic-trunc.mir
AMDGPU/GlobalISel: Legalize some 16-bit round instructions
2019-12-24 09:53:01 -05:00
legalize-inttoptr.mir
AMDGPU/GlobalISel: Add some missing tests for non-power-of-2 cases
2020-02-16 22:48:42 -05:00
legalize-jump-table.mir
Revert "Revert "Reland "[Support] make report_fatal_error abort instead of exit"""
2020-02-13 10:16:06 -08:00
legalize-llvm.amdgcn.image.load.2d.d16.ll
AMDGPU/GlobalISel: Prefer merge/unmerge ops to legalize TFE
2020-02-05 12:56:10 -05:00
legalize-llvm.amdgcn.image.load.2d.ll
AMDGPU/GlobalISel: Prefer merge/unmerge ops to legalize TFE
2020-02-05 12:56:10 -05:00
legalize-llvm.amdgcn.image.store.2d.d16.ll
AMDGPU/GlobalISel: Legalize unpacked d16 image operations
2020-01-30 08:36:11 -05:00
legalize-llvm.amdgcn.s.buffer.load.mir
AMDGPU/GlobalISel: Add mem operand to s.buffer.load intrinsic
2020-02-05 15:04:42 -05:00
legalize-load-constant-32bit.mir
AMDGPU/GlobalISel: Regenerate check lines
2020-01-02 16:00:45 -05:00
legalize-load-constant.mir
AMDGPU/GlobalISel: Widen non-power-of-2 load results
2020-02-12 09:35:10 -05:00
legalize-load-flat.mir
AMDGPU/GlobalISel: Widen non-power-of-2 load results
2020-02-12 09:35:10 -05:00
legalize-load-global.mir
AMDGPU/GlobalISel: Widen non-power-of-2 load results
2020-02-12 09:35:10 -05:00
legalize-load-local.mir
AMDGPU/GlobalISel: Widen non-power-of-2 load results
2020-02-12 09:35:10 -05:00
legalize-load-private.mir
AMDGPU/GlobalISel: Widen non-power-of-2 load results
2020-02-12 09:35:10 -05:00
legalize-lshr.mir
GlobalISel: Allow CSE of G_IMPLICIT_DEF
2020-02-05 17:47:21 -05:00
legalize-merge-values-build-vector.mir
…
legalize-merge-values.mir
GlobalISel: Allow CSE of G_IMPLICIT_DEF
2020-02-05 17:47:21 -05:00
legalize-mul.mir
AMDGPU/GlobalISel: Fix non-pow-2 add/sub/mul for 16-bit insts
2020-02-06 21:43:54 -05:00
legalize-or.mir
GlobalISel: Allow CSE of G_IMPLICIT_DEF
2020-02-05 17:47:21 -05:00
legalize-phi.mir
GlobalISel: Allow CSE of G_IMPLICIT_DEF
2020-02-05 17:47:21 -05:00
legalize-ptr-add.mir
AMDGPU/GlobalISel: Legalize G_PTR_ADD for arbitrary pointers
2020-01-21 16:35:36 -05:00
legalize-ptrtoint.mir
AMDGPU/GlobalISel: Add some missing tests for non-power-of-2 cases
2020-02-16 22:48:42 -05:00
legalize-saddo.mir
AMDGPU/GlobalISel: Legalize G_SEXT_INREG
2020-02-04 13:23:53 -08:00
legalize-sdiv.mir
AMDGPU/GlobalISel: Custom lower 32-bit G_SDIV/G_SREM
2020-02-17 15:09:51 -05:00
legalize-select.mir
GlobalISel: Allow CSE of G_IMPLICIT_DEF
2020-02-05 17:47:21 -05:00
legalize-sext-inreg.mir
AMDGPU/GlobalISel: Don't use legal v2s16 G_BUILD_VECTOR
2020-02-05 11:52:18 -05:00
legalize-sext.mir
AMDGPU/GlobalISel: Legalize G_SEXT_INREG
2020-02-04 13:23:53 -08:00
legalize-sextload-flat.mir
AMDGPU/GlobalISel: Legalize G_SEXT_INREG
2020-02-04 13:23:53 -08:00
legalize-sextload-global.mir
GlobalISel: Support narrowing zextload/sextload
2019-01-22 19:02:10 +00:00
legalize-sextload-local.mir
GlobalISel: Support narrowing zextload/sextload
2019-01-22 19:02:10 +00:00
legalize-sextload-private.mir
GlobalISel: Support narrowing zextload/sextload
2019-01-22 19:02:10 +00:00
legalize-shl.mir
GlobalISel: Allow CSE of G_IMPLICIT_DEF
2020-02-05 17:47:21 -05:00
legalize-shuffle-vector.mir
GlobalISel: Allow CSE of G_IMPLICIT_DEF
2020-02-05 17:47:21 -05:00
legalize-shuffle-vector.s16.mir
GlobalISel: Allow CSE of G_IMPLICIT_DEF
2020-02-05 17:47:21 -05:00
legalize-sitofp.mir
AMDGPU/GlobalISel: Fix non-power-of-2 G_SITOFP/G_UITOFP
2020-02-16 22:48:57 -05:00
legalize-smax.mir
GlobalISel: Allow CSE of G_IMPLICIT_DEF
2020-02-05 17:47:21 -05:00
legalize-smin.mir
GlobalISel: Allow CSE of G_IMPLICIT_DEF
2020-02-05 17:47:21 -05:00
legalize-smulh.mir
AMDGPU/GlobalISel: Legalize smulh/umulh and scalarize mul
2019-01-25 03:23:04 +00:00
legalize-srem.mir
AMDGPU/GlobalISel: Custom lower 32-bit G_SDIV/G_SREM
2020-02-17 15:09:51 -05:00
legalize-ssubo.mir
AMDGPU/GlobalISel: Legalize G_SEXT_INREG
2020-02-04 13:23:53 -08:00
legalize-store-global.mir
AMDGPU/GlobalISel: Widen non-power-of-2 load results
2020-02-12 09:35:10 -05:00
legalize-store.mir
AMDGPU/GlobalISel: Widen non-power-of-2 load results
2020-02-12 09:35:10 -05:00
legalize-sub.mir
AMDGPU/GlobalISel: Fix non-pow-2 add/sub/mul for 16-bit insts
2020-02-06 21:43:54 -05:00
legalize-trunc.mir
AMDGPU/GlobalISel: Make G_TRUNC legal
2020-02-13 15:25:52 -05:00
legalize-uaddo.mir
[GlobalISel] Enable CSE in the IRTranslator & legalizer for -O0 with constants only.
2019-04-15 05:04:20 +00:00
legalize-udiv.mir
AMDGPU/GlobalISel: Custom lower 32-bit G_UDIV/G_UREM
2020-02-17 11:05:50 -08:00
legalize-uitofp.mir
AMDGPU/GlobalISel: Fix non-power-of-2 G_SITOFP/G_UITOFP
2020-02-16 22:48:57 -05:00
legalize-umax.mir
GlobalISel: Allow CSE of G_IMPLICIT_DEF
2020-02-05 17:47:21 -05:00
legalize-umin.mir
GlobalISel: Allow CSE of G_IMPLICIT_DEF
2020-02-05 17:47:21 -05:00
legalize-umulh.mir
AMDGPU/GlobalISel: Legalize smulh/umulh and scalarize mul
2019-01-25 03:23:04 +00:00
legalize-unmerge-values-xfail.mir
Revert "Revert "Reland "[Support] make report_fatal_error abort instead of exit"""
2020-02-13 10:16:06 -08:00
legalize-unmerge-values.mir
GlobalISel: Allow CSE of G_IMPLICIT_DEF
2020-02-05 17:47:21 -05:00
legalize-urem.mir
AMDGPU/GlobalISel: Custom lower 32-bit G_UDIV/G_UREM
2020-02-17 11:05:50 -08:00
legalize-usubo.mir
[GlobalISel] Enable CSE in the IRTranslator & legalizer for -O0 with constants only.
2019-04-15 05:04:20 +00:00
legalize-xor.mir
GlobalISel: Allow CSE of G_IMPLICIT_DEF
2020-02-05 17:47:21 -05:00
legalize-zext.mir
AMDGPU/GlobalISel: Remove extension legality hacks
2020-02-04 12:50:47 -08:00
legalize-zextload-flat.mir
[MIPS GlobalISel] Select any extending load and truncating store
2019-02-08 14:27:23 +00:00
legalize-zextload-global.mir
GlobalISel: Support narrowing zextload/sextload
2019-01-22 19:02:10 +00:00
legalize-zextload-local.mir
GlobalISel: Support narrowing zextload/sextload
2019-01-22 19:02:10 +00:00
legalize-zextload-private.mir
GlobalISel: Support narrowing zextload/sextload
2019-01-22 19:02:10 +00:00
lit.local.cfg
…
llvm.amdgcn.atomic.dec.ll
[AMDGPU][GlobalISel] Refactor selectDS1Addr1Offset/selectDS64Bit4ByteAligned
2020-02-11 16:57:13 -08:00
llvm.amdgcn.atomic.inc.ll
[AMDGPU][GlobalISel] Refactor selectDS1Addr1Offset/selectDS64Bit4ByteAligned
2020-02-11 16:57:13 -08:00
llvm.amdgcn.dispatch.id.ll
AMDGPU/GlobalISel: Handle more input argument intrinsics
2019-07-01 18:50:50 +00:00
llvm.amdgcn.dispatch.ptr.ll
AMDGPU/GlobalISel: Handle more input argument intrinsics
2019-07-01 18:50:50 +00:00
llvm.amdgcn.ds.append.ll
AMDGPU/GlobalISel: Initial selection of MUBUF addr64 load/store
2020-01-27 07:13:56 -08:00
llvm.amdgcn.ds.consume.ll
AMDGPU/GlobalISel: Initial selection of MUBUF addr64 load/store
2020-01-27 07:13:56 -08:00
llvm.amdgcn.ds.gws.barrier.ll
AMDGPU/GlobalISel: Select DS GWS intrinsics
2020-01-16 11:25:10 -05:00
llvm.amdgcn.ds.gws.init.ll
AMDGPU/GlobalISel: Select DS GWS intrinsics
2020-01-16 11:25:10 -05:00
llvm.amdgcn.ds.gws.sema.br.ll
AMDGPU/GlobalISel: Select DS GWS intrinsics
2020-01-16 11:25:10 -05:00
llvm.amdgcn.ds.gws.sema.release.all.ll
Revert "Revert "Reland "[Support] make report_fatal_error abort instead of exit"""
2020-02-13 10:16:06 -08:00
llvm.amdgcn.ds.gws.sema.v.ll
AMDGPU/GlobalISel: Select DS GWS intrinsics
2020-01-16 11:25:10 -05:00
llvm.amdgcn.ds.ordered.add.gfx10.ll
AMDGPU/GlobalISel: Select llvm.amdgcn.ds.ordered.{add|swap}
2020-01-13 13:09:38 -05:00
llvm.amdgcn.ds.ordered.add.ll
AMDGPU/GlobalISel: Select llvm.amdgcn.ds.ordered.{add|swap}
2020-01-13 13:09:38 -05:00
llvm.amdgcn.ds.ordered.swap.ll
AMDGPU/GlobalISel: Select llvm.amdgcn.ds.ordered.{add|swap}
2020-01-13 13:09:38 -05:00
llvm.amdgcn.end.cf.i32.ll
AMDGPU/GlobalISel: Add pre-legalize combiner pass
2020-01-22 10:16:39 -05:00
llvm.amdgcn.end.cf.i64.ll
AMDGPU/GlobalISel: Add pre-legalize combiner pass
2020-01-22 10:16:39 -05:00
llvm.amdgcn.fdot2.ll
AMDGPU/GlobalISel: Select llvm.amdgcn.fdot2
2020-02-21 13:35:40 -05:00
llvm.amdgcn.fmul.legacy.ll
AMDGPU/GlobalISel: Select llvm.amdgcn.fmul.legacy
2020-02-21 10:30:26 -05:00
llvm.amdgcn.if.break.i32.ll
AMDGPU/GlobalISel: Replace handling of boolean values
2020-01-06 18:26:42 -05:00
llvm.amdgcn.if.break.i64.ll
AMDGPU/GlobalISel: Replace handling of boolean values
2020-01-06 18:26:42 -05:00
llvm.amdgcn.implicit.buffer.ptr.ll
AMDGPU/GlobalISel: Handle more input argument intrinsics
2019-07-01 18:50:50 +00:00
llvm.amdgcn.init.exec.ll
AMDGPU/GlobalISel: Add support for init.exec intrinsics
2019-10-01 02:07:25 +00:00
llvm.amdgcn.init.exec.wave32.ll
AMDGPU/GlobalISel: Add support for init.exec intrinsics
2019-10-01 02:07:25 +00:00
llvm.amdgcn.interp.p1.f16.ll
AMDGPU/GlobalISel: Handle 16-bank LDS llvm.amdgcn.interp.p1.f16
2020-01-22 12:10:59 -05:00
llvm.amdgcn.is.private.ll
AMDGPU/GlobalISel: Only map VOP operands to VGPRs
2020-01-30 08:32:35 -05:00
llvm.amdgcn.is.shared.ll
AMDGPU/GlobalISel: Only map VOP operands to VGPRs
2020-01-30 08:32:35 -05:00
llvm.amdgcn.kernarg.segment.ptr.ll
AMDGPU/GlobalISel: Initial selection of MUBUF addr64 load/store
2020-01-27 07:13:56 -08:00
llvm.amdgcn.mov.dpp8.ll
AMDGPU/GlobalISel: Select llvm.amdgcn.mov.dpp8
2020-01-22 11:43:40 -05:00
llvm.amdgcn.mov.dpp.ll
AMDGPU/GlobalISel: Select llvm.amdgcn.mov.dpp
2020-01-22 11:43:53 -05:00
llvm.amdgcn.permlane.ll
AMDGPU/GlobalISel: Select permlane16/permlanex16
2020-01-29 17:55:31 -05:00
llvm.amdgcn.queue.ptr.ll
AMDGPU/GlobalISel: Handle more input argument intrinsics
2019-07-01 18:50:50 +00:00
llvm.amdgcn.raw.buffer.atomic.add.ll
AMDGPU/GlobalISel: Select buffer atomics
2020-01-27 15:16:44 -05:00
llvm.amdgcn.raw.buffer.atomic.cmpswap.ll
AMDGPU/GlobalISel: Select llvm.amdgcn.buffer.atomic.cmpswap
2020-01-30 08:22:43 -05:00
llvm.amdgcn.raw.buffer.load.format.f16.ll
AMDGPU/GlobalISel: Don't use legal v2s16 G_BUILD_VECTOR
2020-02-05 11:52:18 -05:00
llvm.amdgcn.raw.buffer.load.format.ll
AMDGPU/GlobalISel: Select llvm.amdgcn.raw.buffer.load.format
2020-01-27 13:02:19 -05:00
llvm.amdgcn.raw.buffer.load.ll
AMDGPU/GlobalISel: Select G_SEXT_INREG
2020-02-04 13:23:53 -08:00
llvm.amdgcn.raw.buffer.store.format.f16.ll
AMDGPU/GlobalISel: Move llvm.amdgcn.raw.buffer.store handling
2020-01-27 14:59:30 -05:00
llvm.amdgcn.raw.buffer.store.format.f32.ll
AMDGPU/GlobalISel: Move llvm.amdgcn.raw.buffer.store handling
2020-01-27 14:59:30 -05:00
llvm.amdgcn.raw.buffer.store.ll
AMDGPU/GlobalISel: Move llvm.amdgcn.raw.buffer.store handling
2020-01-27 14:59:30 -05:00
llvm.amdgcn.raw.tbuffer.load.f16.ll
AMDGPU/GlobalISel: Don't use legal v2s16 G_BUILD_VECTOR
2020-02-05 11:52:18 -05:00
llvm.amdgcn.raw.tbuffer.load.ll
AMDGPU/GlobalISel: Select llvm.amdgcn.raw.tbuffer.load
2020-01-27 13:40:37 -05:00
llvm.amdgcn.s.buffer.load.ll
GlobalISel: Allow running localizer earlier
2020-02-17 11:24:06 -08:00
llvm.amdgcn.s.sleep.ll
Reapply r372285 "GlobalISel: Don't materialize immarg arguments to intrinsics"
2019-09-19 16:26:14 +00:00
llvm.amdgcn.sbfe.ll
AMDGPU/GlobalISel: Handle sbfe/ubfe intrinsic
2020-02-17 09:20:13 -05:00
llvm.amdgcn.sdot2.ll
AMDGPU: Move dot intrinsic patterns to instruction def
2020-02-21 13:35:40 -05:00
llvm.amdgcn.sdot4.ll
AMDGPU: Move dot intrinsic patterns to instruction def
2020-02-21 13:35:40 -05:00
llvm.amdgcn.sdot8.ll
AMDGPU: Move dot intrinsic patterns to instruction def
2020-02-21 13:35:40 -05:00
llvm.amdgcn.softwqm.ll
AMDGPU/GlobalISel: Select wqm, softwqm and wwm intrinsics
2020-01-24 13:06:44 -08:00
llvm.amdgcn.struct.buffer.atomic.add.ll
AMDGPU/GlobalISel: Select buffer atomics
2020-01-27 15:16:44 -05:00
llvm.amdgcn.struct.buffer.atomic.cmpswap.ll
AMDGPU/GlobalISel: Select llvm.amdgcn.buffer.atomic.cmpswap
2020-01-30 08:22:43 -05:00
llvm.amdgcn.struct.buffer.load.format.f16.ll
AMDGPU/GlobalISel: Don't use legal v2s16 G_BUILD_VECTOR
2020-02-05 11:52:18 -05:00
llvm.amdgcn.struct.buffer.load.format.ll
AMDGPU/GlobalISel: Select llvm.amdgcn.struct.buffer.load.format
2020-01-27 13:23:35 -05:00
llvm.amdgcn.struct.buffer.load.ll
AMDGPU/GlobalISel: Select G_SEXT_INREG
2020-02-04 13:23:53 -08:00
llvm.amdgcn.struct.buffer.store.format.f16.ll
AMDGPU/GlobalISel: Select llvm.amdgcn.struct.buffer.store[.format]
2020-01-27 15:00:21 -05:00
llvm.amdgcn.struct.buffer.store.format.f32.ll
AMDGPU/GlobalISel: Select llvm.amdgcn.struct.buffer.store[.format]
2020-01-27 15:00:21 -05:00
llvm.amdgcn.struct.buffer.store.ll
AMDGPU/GlobalISel: Select llvm.amdgcn.struct.buffer.store[.format]
2020-01-27 15:00:21 -05:00
llvm.amdgcn.struct.tbuffer.load.f16.ll
AMDGPU/GlobalISel: Don't use legal v2s16 G_BUILD_VECTOR
2020-02-05 11:52:18 -05:00
llvm.amdgcn.struct.tbuffer.load.ll
AMDGPU/GlobalISel: Select llvm.amdcn.struct.tbuffer.load
2020-01-27 14:42:04 -05:00
llvm.amdgcn.ubfe.ll
AMDGPU/GlobalISel: Handle sbfe/ubfe intrinsic
2020-02-17 09:20:13 -05:00
llvm.amdgcn.udot2.ll
AMDGPU: Move dot intrinsic patterns to instruction def
2020-02-21 13:35:40 -05:00
llvm.amdgcn.udot4.ll
AMDGPU: Move dot intrinsic patterns to instruction def
2020-02-21 13:35:40 -05:00
llvm.amdgcn.udot8.ll
AMDGPU: Move dot intrinsic patterns to instruction def
2020-02-21 13:35:40 -05:00
llvm.amdgcn.update.dpp.ll
[AMDGPU] fixed divergence driven shift operations selection
2020-01-31 20:49:56 +03:00
llvm.amdgcn.workgroup.id.ll
AMDGPU/GlobalISel: Remove manual store select code
2019-08-01 03:52:40 +00:00
llvm.amdgcn.workitem.id.ll
AMDGPU/GlobalISel: Initial selection of MUBUF addr64 load/store
2020-01-27 07:13:56 -08:00
llvm.amdgcn.wqm.ll
AMDGPU/GlobalISel: Select wqm, softwqm and wwm intrinsics
2020-01-24 13:06:44 -08:00
llvm.amdgcn.wqm.vote.ll
AMDGPU/GlobalISel: Select llvm.amdgcn.wqm.vote
2020-01-07 10:15:29 -05:00
llvm.amdgcn.wwm.ll
AMDGPU/GlobalISel: Select wqm, softwqm and wwm intrinsics
2020-01-24 13:06:44 -08:00
localizer.ll
GlobalISel: Allow running localizer earlier
2020-02-17 11:24:06 -08:00
memory-legalizer-atomic-fence.ll
AMDGPU/GlobalISel: Select G_FENCE
2019-07-02 14:17:38 +00:00
mubuf-global.ll
AMDGPU/GlobalISel: Select MUBUF path for global atomic cmpxchg
2020-02-19 06:19:22 -08:00
no-legalize-atomic.mir
GlobalISel: Don't reduce elements for atomic load/store
2019-01-27 22:36:24 +00:00
read_register.ll
GlobalISel: Handle llvm.read_register
2020-01-09 17:37:52 -05:00
readcyclecounter.ll
AMDGPU/GlobalISel: Legalize G_READCYCLECOUNTER
2020-01-06 19:16:32 -05:00
regbankselect-add.mir
AMDGPU/GlobalISel: Only map VOP operands to VGPRs
2020-01-30 08:32:35 -05:00
regbankselect-amdgcn-exp-compr.mir
AMDGPU/GlobalISel: Fix RegBanKSelect for llvm.amdgcn.exp.compr
2020-01-23 13:30:46 -08:00
regbankselect-amdgcn-exp.mir
Reapply r372285 "GlobalISel: Don't materialize immarg arguments to intrinsics"
2019-09-19 16:26:14 +00:00
regbankselect-amdgcn-s-buffer-load.mir
AMDGPU/GlobalISel: Fix move s.buffer.load to VALU
2020-02-07 07:19:01 -08:00
regbankselect-amdgcn.class.mir
AMDGPU/GlobalISel: Only map VOP operands to VGPRs
2020-01-30 08:32:35 -05:00
regbankselect-amdgcn.cvt.pkrtz.mir
AMDGPU/GlobalISel: Only map VOP operands to VGPRs
2020-01-30 08:32:35 -05:00
regbankselect-amdgcn.div.fmas.mir
AMDGPU/GlobalISel: Fix mapping G_ICMP with constrained result
2020-02-12 16:19:45 -08:00
regbankselect-amdgcn.div.scale.mir
AMDGPU/GlobalISel: Only map VOP operands to VGPRs
2020-01-30 08:32:35 -05:00
regbankselect-amdgcn.ds.append.mir
AMDGPU/GlobalISel: Select DS append/consume
2020-01-17 20:09:53 -05:00
regbankselect-amdgcn.ds.bpermute.mir
AMDGPU/GlobalISel: RegBankSelect for some DS intrinsics
2019-06-29 00:33:13 +00:00
regbankselect-amdgcn.ds.consume.mir
AMDGPU/GlobalISel: Select DS append/consume
2020-01-17 20:09:53 -05:00
regbankselect-amdgcn.ds.fmax.mir
AMDGPU/GlobalISel: RegBankSelect for some DS intrinsics
2019-06-29 00:33:13 +00:00
regbankselect-amdgcn.ds.fmin.mir
AMDGPU/GlobalISel: RegBankSelect for some DS intrinsics
2019-06-29 00:33:13 +00:00
regbankselect-amdgcn.ds.gws.init.mir
AMDGPU/GlobalISel: Copy type when inserting readfirstlane
2020-01-12 22:44:51 -05:00
regbankselect-amdgcn.ds.gws.sema.v.mir
AMDGPU/GlobalISel: Copy type when inserting readfirstlane
2020-01-12 22:44:51 -05:00
regbankselect-amdgcn.ds.ordered.add.mir
AMDGPU/GlobalISel: Copy type when inserting readfirstlane
2020-01-12 22:44:51 -05:00
regbankselect-amdgcn.ds.ordered.swap.mir
AMDGPU/GlobalISel: Copy type when inserting readfirstlane
2020-01-12 22:44:51 -05:00
regbankselect-amdgcn.ds.permute.mir
AMDGPU/GlobalISel: RegBankSelect for some DS intrinsics
2019-06-29 00:33:13 +00:00
regbankselect-amdgcn.ds.swizzle.mir
Reapply r372285 "GlobalISel: Don't materialize immarg arguments to intrinsics"
2019-09-19 16:26:14 +00:00
regbankselect-amdgcn.else.32.mir
AMDGPU/GlobalISel: Fix RegBankSelect for amdgcn.else
2019-09-13 03:55:49 +00:00
regbankselect-amdgcn.else.64.mir
AMDGPU/GlobalISel: Fix RegBankSelect for amdgcn.else
2019-09-13 03:55:49 +00:00
regbankselect-amdgcn.fcmp.mir
AMDGPU/GlobalISel: Only map VOP operands to VGPRs
2020-01-30 08:32:35 -05:00
regbankselect-amdgcn.fmul.legacy.mir
AMDGPU/GlobalISel: Only map VOP operands to VGPRs
2020-01-30 08:32:35 -05:00
regbankselect-amdgcn.groupstaticsize.mir
AMDGPU/GlobalISel: RegBankSelect for some simple leaf intrinsics
2019-06-29 00:22:28 +00:00
regbankselect-amdgcn.icmp.mir
AMDGPU/GlobalISel: Only map VOP operands to VGPRs
2020-01-30 08:32:35 -05:00
regbankselect-amdgcn.image.load.1d.ll
AMDPGPU/GlobalISel: Select more MUBUF global addressing modes
2020-01-27 07:28:36 -08:00
regbankselect-amdgcn.image.sample.1d.ll
AMDPGPU/GlobalISel: Select more MUBUF global addressing modes
2020-01-27 07:28:36 -08:00
regbankselect-amdgcn.interp.mov.mir
AMDGPU/GlobalISel: RegBankSelect interp intrinsics
2020-01-22 09:01:34 -05:00
regbankselect-amdgcn.interp.p1.f16.mir
AMDGPU/GlobalISel: RegBankSelect interp intrinsics
2020-01-22 09:01:34 -05:00
regbankselect-amdgcn.interp.p1.mir
AMDGPU/GlobalISel: RegBankSelect interp intrinsics
2020-01-22 09:01:34 -05:00
regbankselect-amdgcn.interp.p2.f16.mir
AMDGPU/GlobalISel: RegBankSelect interp intrinsics
2020-01-22 09:01:34 -05:00
regbankselect-amdgcn.interp.p2.mir
AMDGPU/GlobalISel: RegBankSelect interp intrinsics
2020-01-22 09:01:34 -05:00
regbankselect-amdgcn.kernarg.segment.ptr.mir
…
regbankselect-amdgcn.kill.mir
AMDGPU/GlobalISel: Replace handling of boolean values
2020-01-06 18:26:42 -05:00
regbankselect-amdgcn.mfma.mir
AMDGPU/GlobalISel: Add AGPR bank and RegBankSelect mfma intrinsics
2019-12-01 22:15:48 -08:00
regbankselect-amdgcn.ps.live.mir
AMDDGPU/GlobalISel: Fix RegBankSelect for llvm.amdgcn.ps.live
2020-01-20 23:21:53 -05:00
regbankselect-amdgcn.raw.buffer.load.ll
AMDGPU/GlobalISel: Select llvm.amdgcn.raw.buffer.load
2020-01-27 12:49:23 -05:00
regbankselect-amdgcn.readfirstlane.mir
AMDGPU/GlobalISel: RegBankSelect for readlane/readfirstlane
2019-07-01 16:19:39 +00:00
regbankselect-amdgcn.readlane.mir
AMDGPU/GlobalISel: Copy type when inserting readfirstlane
2020-01-12 22:44:51 -05:00
regbankselect-amdgcn.s.buffer.load.ll
AMDGPU/GlobalISel: Widen non-power-of-2 load results
2020-02-12 09:35:10 -05:00
regbankselect-amdgcn.s.buffer.load.mir
AMDGPU/GlobalISel: Fix move s.buffer.load to VALU
2020-02-07 07:19:01 -08:00
regbankselect-amdgcn.s.get.waveid.in.workgroup.mir
AMDGPU/GlobalISel: RegBankSelect for some simple leaf intrinsics
2019-06-29 00:22:28 +00:00
regbankselect-amdgcn.s.getpc.mir
AMDGPU/GlobalISel: RegBankSelect for some simple leaf intrinsics
2019-06-29 00:22:28 +00:00
regbankselect-amdgcn.s.getreg.mir
AMDGPU/GlobalISel: RegBankSelect for some simple leaf intrinsics
2019-06-29 00:22:28 +00:00
regbankselect-amdgcn.s.memrealtime.mir
AMDGPU/GlobalISel: RegBankSelect for some simple leaf intrinsics
2019-06-29 00:22:28 +00:00
regbankselect-amdgcn.s.memtime.mir
AMDGPU/GlobalISel: RegBankSelect for some simple leaf intrinsics
2019-06-29 00:22:28 +00:00
regbankselect-amdgcn.s.sendmsg.mir
AMDGPU/GlobalISel: Copy type when inserting readfirstlane
2020-01-12 22:44:51 -05:00
regbankselect-amdgcn.s.sendmsghalt.mir
AMDGPU/GlobalISel: Copy type when inserting readfirstlane
2020-01-12 22:44:51 -05:00
regbankselect-amdgcn.struct.buffer.load.ll
AMDGPU/GlobalISel: Select llvm.amdgcn.struct.buffer.load
2020-01-27 13:05:55 -05:00
regbankselect-amdgcn.struct.buffer.store.ll
AMDGPU/GlobalISel: Select llvm.amdgcn.struct.buffer.store[.format]
2020-01-27 15:00:21 -05:00
regbankselect-amdgcn.update.dpp.mir
AMDGPU/GlobalISel: RegBankSelect for update.dpp
2019-06-29 00:44:36 +00:00
regbankselect-amdgcn.wqm.mir
AMDGPU/GlobalISel: Select wqm, softwqm and wwm intrinsics
2020-01-24 13:06:44 -08:00
regbankselect-amdgcn.wqm.vote.mir
AMDGPU/GlobalISel: Replace handling of boolean values
2020-01-06 18:26:42 -05:00
regbankselect-amdgcn.writelane.mir
AMDGPU/GlobalISel: Copy type when inserting readfirstlane
2020-01-12 22:44:51 -05:00
regbankselect-amdgcn.wwm.mir
AMDGPU/GlobalISel: Select wqm, softwqm and wwm intrinsics
2020-01-24 13:06:44 -08:00
regbankselect-amdgpu-ffbh-u32.mir
AMDGPU/GlobalISel: Only map VOP operands to VGPRs
2020-01-30 08:32:35 -05:00
regbankselect-and-s1.mir
AMDGPU/GlobalISel: Fix mapping G_ICMP with constrained result
2020-02-12 16:19:45 -08:00
regbankselect-and.mir
AMDGPU/GlobalISel: Only map VOP operands to VGPRs
2020-01-30 08:32:35 -05:00
regbankselect-anyext.mir
AMDGPU/GlobalISel: Fix forming G_TRUNC with vcc result
2020-01-31 20:29:41 -05:00
regbankselect-ashr.mir
AMDGPU/GlobalISel: Only map VOP operands to VGPRs
2020-01-30 08:32:35 -05:00
regbankselect-atomic-cmpxchg.mir
AMDGPU/GlobalISel: Legality/regbankselect for atomicrmw/atomic_cmpxchg
2018-12-20 00:33:49 +00:00
regbankselect-atomicrmw-add.mir
AMDGPU/GlobalISel: Legality/regbankselect for atomicrmw/atomic_cmpxchg
2018-12-20 00:33:49 +00:00
regbankselect-atomicrmw-and.mir
AMDGPU/GlobalISel: Fix broken tests
2019-07-22 13:33:11 +00:00
regbankselect-atomicrmw-fadd.mir
AMDGPU/GlobalISel: Handle G_ATOMICRMW_FADD
2019-08-01 03:33:15 +00:00
regbankselect-atomicrmw-max.mir
AMDGPU/GlobalISel: Fix broken tests
2019-07-22 13:33:11 +00:00
regbankselect-atomicrmw-min.mir
AMDGPU/GlobalISel: Fix broken tests
2019-07-22 13:33:11 +00:00
regbankselect-atomicrmw-or.mir
AMDGPU/GlobalISel: Fix broken tests
2019-07-22 13:33:11 +00:00
regbankselect-atomicrmw-sub.mir
AMDGPU/GlobalISel: Fix broken tests
2019-07-22 13:33:11 +00:00
regbankselect-atomicrmw-umax.mir
AMDGPU/GlobalISel: Fix broken tests
2019-07-22 13:33:11 +00:00
regbankselect-atomicrmw-umin.mir
AMDGPU/GlobalISel: Fix broken tests
2019-07-22 13:33:11 +00:00
regbankselect-atomicrmw-xchg.mir
AMDGPU/GlobalISel: Fix broken tests
2019-07-22 13:33:11 +00:00
regbankselect-atomicrmw-xor.mir
AMDGPU/GlobalISel: Fix broken tests
2019-07-22 13:33:11 +00:00
regbankselect-bitcast.mir
…
regbankselect-bitreverse.mir
AMDGPU/GlobalISel: Select G_BITREVERSE
2019-09-04 20:46:31 +00:00
regbankselect-block-addr.mir
[Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing
2019-09-11 11:16:48 +00:00
regbankselect-brcond.mir
AMDGPU/GlobalISel: Fix forming G_TRUNC with vcc result
2020-01-31 20:29:41 -05:00
regbankselect-bswap.mir
AMDGPU/GlobalISel: Handle G_BSWAP
2020-02-14 09:09:44 -08:00
regbankselect-build-vector-trunc.mir
AMDGPU/GlobalISel: Legalize G_BUILD_VECTOR_TRUNC
2019-09-09 17:04:18 +00:00
regbankselect-build-vector-trunc.v2s16.mir
AMDGPU/GlobalISel: Don't use legal v2s16 G_BUILD_VECTOR
2020-02-05 11:52:18 -05:00
regbankselect-build-vector.mir
AMDGPU/GlobalISel: Fix RegBankSelect for G_BUILD_VECTOR
2019-07-01 13:40:17 +00:00
regbankselect-concat-vector.mir
AMDGPU/GlobalISel: RegBankSelect for G_CONCAT_VECTORS
2019-07-15 17:20:40 +00:00
regbankselect-constant.mir
AMDGPU/GlobalISel: Fix RegBankSelect for sendmsg intrinsics
2019-10-06 01:37:34 +00:00
regbankselect-ctlz-zero-undef.mir
GlobalISel: Fix narrowScalar for G_{CTLZ|CTTZ}_ZERO_UNDEF
2020-02-09 19:02:38 -05:00
regbankselect-ctpop.mir
AMDGPU/GlobalISel: Split 64-bit G_CTPOP in RegBankSelect
2020-02-09 18:39:33 -05:00
regbankselect-cttz-zero-undef.mir
GlobalISel: Fix narrowScalar for G_{CTLZ|CTTZ}_ZERO_UNDEF
2020-02-09 19:02:38 -05:00
regbankselect-default.mir
GlobalISel: Enforce operand types for constants
2019-02-04 23:29:31 +00:00
regbankselect-extract-vector-elt.mir
AMDGPU/GlobalISel: Fold constant offset vector extract indexes
2020-01-22 10:50:59 -05:00
regbankselect-extract.mir
AMDGPU/GlobalISel: Fix RegBankSelect for 1024-bit values
2019-10-02 01:02:14 +00:00
regbankselect-fabs.mir
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regbankselect-fadd.mir
AMDGPU/GlobalISel: Only map VOP operands to VGPRs
2020-01-30 08:32:35 -05:00
regbankselect-fcanonicalize.mir
AMDGPU/GlobalISel: Only map VOP operands to VGPRs
2020-01-30 08:32:35 -05:00
regbankselect-fceil.mir
AMDGPU/GlobalISel: Only map VOP operands to VGPRs
2020-01-30 08:32:35 -05:00
regbankselect-fcmp.mir
AMDGPU/GlobalISel: Introduce vcc reg bank
2019-01-08 06:30:53 +00:00
regbankselect-fexp2.mir
AMDGPU/GlobalISel: Only map VOP operands to VGPRs
2020-01-30 08:32:35 -05:00
regbankselect-flog2.mir
AMDGPU/GlobalISel: Only map VOP operands to VGPRs
2020-01-30 08:32:35 -05:00
regbankselect-fma.mir
AMDGPU/GlobalISel: Only map VOP operands to VGPRs
2020-01-30 08:32:35 -05:00
regbankselect-fmul.mir
AMDGPU/GlobalISel: Only map VOP operands to VGPRs
2020-01-30 08:32:35 -05:00
regbankselect-fneg.mir
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regbankselect-fpext.mir
AMDGPU/GlobalISel: Only map VOP operands to VGPRs
2020-01-30 08:32:35 -05:00
regbankselect-fptosi.mir
AMDGPU/GlobalISel: Only map VOP operands to VGPRs
2020-01-30 08:32:35 -05:00
regbankselect-fptoui.mir
AMDGPU/GlobalISel: Only map VOP operands to VGPRs
2020-01-30 08:32:35 -05:00
regbankselect-fptrunc.mir
AMDGPU/GlobalISel: Only map VOP operands to VGPRs
2020-01-30 08:32:35 -05:00
regbankselect-frame-index.mir
AMDGPU/GlobalISel: Assume VGPR for G_FRAME_INDEX
2019-10-02 01:02:24 +00:00
regbankselect-frint.mir
AMDGPU/GlobalISel: Only map VOP operands to VGPRs
2020-01-30 08:32:35 -05:00
regbankselect-fsqrt.mir
AMDGPU/GlobalISel: Only map VOP operands to VGPRs
2020-01-30 08:32:35 -05:00
regbankselect-fsub.mir
AMDGPU/GlobalISel: Only map VOP operands to VGPRs
2020-01-30 08:32:35 -05:00
regbankselect-icmp.mir
AMDGPU/GlobalISel: Fix mapping G_ICMP with constrained result
2020-02-12 16:19:45 -08:00
regbankselect-icmp.s16.mir
AMDGPU/GlobalISel: Fix mapping G_ICMP with constrained result
2020-02-12 16:19:45 -08:00
regbankselect-illegal-copy.mir
Revert "Revert "Reland "[Support] make report_fatal_error abort instead of exit"""
2020-02-13 10:16:06 -08:00
regbankselect-insert-vector-elt.mir
AMDGPU/GlobalISel: Keep G_BITCAST out of waterfall loop
2020-01-22 11:16:19 -05:00
regbankselect-insert.mir
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regbankselect-intrinsic-trunc.mir
AMDGPU/GlobalISel: Only map VOP operands to VGPRs
2020-01-30 08:32:35 -05:00
regbankselect-inttoptr.mir
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regbankselect-load.mir
AMDGPU/GlobalISel: Refine SMRD selection rules
2020-01-04 12:40:35 -05:00
regbankselect-lshr.mir
AMDGPU/GlobalISel: Only map VOP operands to VGPRs
2020-01-30 08:32:35 -05:00
regbankselect-merge-values.mir
[AMDGPU] Add support for immediate operand for S_ENDPGM
2019-03-12 09:52:58 +00:00
regbankselect-mul.mir
AMDGPU/GlobalISel: Only map VOP operands to VGPRs
2020-01-30 08:32:35 -05:00
regbankselect-or.mir
AMDGPU/GlobalISel: Fix mapping G_ICMP with constrained result
2020-02-12 16:19:45 -08:00
regbankselect-phi-s1.mir
AMDGPU/GlobalISel: Fix mapping G_ICMP with constrained result
2020-02-12 16:19:45 -08:00
regbankselect-phi.mir
AMDGPU/GlobalISel: Fix mapping G_ICMP with constrained result
2020-02-12 16:19:45 -08:00
regbankselect-ptr-add.mir
[globalisel] Rename G_GEP to G_PTR_ADD
2019-11-05 10:31:17 -08:00
regbankselect-ptrtoint.mir
GlobalISel: Verify pointer casts
2019-01-29 23:29:00 +00:00
regbankselect-reg-sequence.mir
Reapply "GlobalISel: Avoid producing Illegal copies in RegBankSelect"
2019-06-15 00:33:26 +00:00
regbankselect-sadde.mir
AMDGPU/GlobalISel: Fix forming G_TRUNC with vcc result
2020-01-31 20:29:41 -05:00
regbankselect-select.mir
AMDGPU/GlobalISel: Fix forming G_TRUNC with vcc result
2020-01-31 20:29:41 -05:00
regbankselect-sext-inreg.mir
AMDGPU/GlobalISel: Do a better job splitting 64-bit G_SEXT_INREG
2020-02-04 13:23:53 -08:00
regbankselect-sext.mir
AMDGPU/GlobalISel: Fix forming G_TRUNC with vcc result
2020-01-31 20:29:41 -05:00
regbankselect-sextload.mir
AMDPGPU/GlobalISel: Select more MUBUF global addressing modes
2020-01-27 07:28:36 -08:00
regbankselect-shl.mir
AMDGPU/GlobalISel: Only map VOP operands to VGPRs
2020-01-30 08:32:35 -05:00
regbankselect-shuffle-vector.mir
AMDGPU/GlobalISel: Fix RegBankSelect for G_SHUFFLE_VECTOR
2020-02-17 15:11:25 -05:00
regbankselect-sitofp.mir
AMDGPU/GlobalISel: Only map VOP operands to VGPRs
2020-01-30 08:32:35 -05:00
regbankselect-smax.mir
AMDGPU/GlobalISel: Fix SALU mapping for v2s16 min/max
2020-02-21 14:02:16 -05:00
regbankselect-smin.mir
AMDGPU/GlobalISel: Fix SALU mapping for v2s16 min/max
2020-02-21 14:02:16 -05:00
regbankselect-smulh.mir
AMDGPU/GlobalISel: Only map VOP operands to VGPRs
2020-01-30 08:32:35 -05:00
regbankselect-ssube.mir
AMDGPU/GlobalISel: Fix forming G_TRUNC with vcc result
2020-01-31 20:29:41 -05:00
regbankselect-sub.mir
AMDGPU/GlobalISel: Only map VOP operands to VGPRs
2020-01-30 08:32:35 -05:00
regbankselect-trunc.mir
AMDGPU/GlobalISel: Fix forming G_TRUNC with vcc result
2020-01-31 20:29:41 -05:00
regbankselect-uadde.mir
AMDGPU/GlobalISel: Fix forming G_TRUNC with vcc result
2020-01-31 20:29:41 -05:00
regbankselect-uaddo.mir
AMDGPU/GlobalISel: Replace handling of boolean values
2020-01-06 18:26:42 -05:00
regbankselect-uitofp.mir
AMDGPU/GlobalISel: Only map VOP operands to VGPRs
2020-01-30 08:32:35 -05:00
regbankselect-umax.mir
AMDGPU/GlobalISel: Fix SALU mapping for v2s16 min/max
2020-02-21 14:02:16 -05:00
regbankselect-umin.mir
AMDGPU/GlobalISel: Fix SALU mapping for v2s16 min/max
2020-02-21 14:02:16 -05:00
regbankselect-umulh.mir
AMDGPU/GlobalISel: Only map VOP operands to VGPRs
2020-01-30 08:32:35 -05:00
regbankselect-unmerge-values.mir
AMDGPU/GlobalISel: InstrMapping for G_UNMERGE_VALUES
2019-01-08 00:46:19 +00:00
regbankselect-usube.mir
AMDGPU/GlobalISel: Fix forming G_TRUNC with vcc result
2020-01-31 20:29:41 -05:00
regbankselect-usubo.mir
AMDGPU/GlobalISel: Replace handling of boolean values
2020-01-06 18:26:42 -05:00
regbankselect-xor.mir
AMDGPU/GlobalISel: Fix mapping G_ICMP with constrained result
2020-02-12 16:19:45 -08:00
regbankselect-zext.mir
AMDGPU/GlobalISel: Fix forming G_TRUNC with vcc result
2020-01-31 20:29:41 -05:00
regbankselect-zextload.mir
AMDPGPU/GlobalISel: Select more MUBUF global addressing modes
2020-01-27 07:28:36 -08:00
regbankselect.mir
AMDPGPU/GlobalISel: Select more MUBUF global addressing modes
2020-01-27 07:28:36 -08:00
ret.ll
AMDGPU/GlobalISel: Handle most function return types
2019-07-26 02:36:05 +00:00
sdiv.i32.ll
AMDGPU/GlobalISel: Custom lower 32-bit G_SDIV/G_SREM
2020-02-17 15:09:51 -05:00
shader-epilogs.ll
AMDGPU/GlobalISel: Remove unnecesssary REQUIREs
2019-05-29 13:14:35 +00:00
smrd.ll
AMDGPU/GlobalISel: Remove unnecesssary REQUIREs
2019-05-29 13:14:35 +00:00
srem.i32.ll
AMDGPU/GlobalISel: Custom lower 32-bit G_SDIV/G_SREM
2020-02-17 15:09:51 -05:00
trunc.ll
AMDGPU/GlobalISel: Select v2s32->v2s16 G_TRUNC
2020-02-17 09:20:13 -05:00
udiv.i32.ll
AMDGPU/GlobalISel: Custom lower 32-bit G_UDIV/G_UREM
2020-02-17 11:05:50 -08:00
urem.i32.ll
AMDGPU/GlobalISel: Custom lower 32-bit G_UDIV/G_UREM
2020-02-17 11:05:50 -08:00
write_register.ll
GlobalISel: Lower G_WRITE_REGISTER
2020-01-29 06:48:24 -08:00
xnor.ll
AMDGPU/GlobalISel: Fix xnor matching
2020-02-21 11:42:49 -05:00