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llvm-project/llvm/lib/Target/AArch64
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Florian Mayer 02dbed4b7f [mte] [nfc] do not keep Tag in AllocaInfo 
this is to get the implementation closer to HWASan

Reviewed By: eugenis

Differential Revision: https://reviews.llvm.org/D118960
2022-02-04 12:34:22 -08:00
..
AsmParser
[llvm] Cleanup header dependencies in ADT and Support
2022-01-21 13:54:49 +01:00
Disassembler
Ensure newlines at the end of files (NFC)
2022-01-06 23:44:02 -08:00
GISel
Reduce dependencies on llvm/BinaryFormat/Dwarf.h
2022-02-04 11:44:03 +01:00
MCTargetDesc
Revert "Rename llvm::array_lengthof into llvm::size to match std::size from C++17"
2022-01-26 16:55:53 +01:00
TargetInfo
Fix shlib builds for all lib/Target/*/TargetInfo libs
2021-10-08 15:21:13 -07:00
Utils
[SVE][CodeGen] Use splice instruction when lowering VECTOR_SPLICE
2022-01-11 11:58:17 +00:00
AArch64.h
[Target] Remove unused forward declarations (NFC)
2022-01-02 10:20:15 -08:00
AArch64.td
[ARM] Add Cortex-X1C Support for Clang and LLVM
2022-01-31 14:23:35 +00:00
AArch64A53Fix835769.cpp
[AArch64] Use Feature for A53 Erratum 835769 Fix
2021-12-10 15:09:59 +00:00
AArch64A57FPLoadBalancing.cpp
…
AArch64AdvSIMDScalarPass.cpp
[llvm] Use range-based for loops (NFC)
2021-12-11 11:29:12 -08:00
AArch64AsmPrinter.cpp
[AArch64][GlobalISel] CodeGen for Armv8.8/9.3 MOPS
2022-01-31 20:54:41 +00:00
AArch64BranchTargets.cpp
…
AArch64CallingConvention.cpp
…
AArch64CallingConvention.h
…
AArch64CallingConvention.td
AArch64: don't claim to preserve registers used by prologue code
2022-01-10 12:27:04 +00:00
AArch64CleanupLocalDynamicTLSPass.cpp
…
AArch64CollectLOH.cpp
…
AArch64Combine.td
[AArch64][GlobalISel] Split vector stores of zero.
2021-12-09 19:04:48 -08:00
AArch64CompressJumpTables.cpp
…
AArch64CondBrTuning.cpp
[llvm] Use range-based for loops (NFC)
2021-11-28 10:04:54 -08:00
AArch64ConditionalCompares.cpp
…
AArch64ConditionOptimizer.cpp
…
AArch64DeadRegisterDefinitionsPass.cpp
…
AArch64ExpandImm.cpp
[llvm] Use range-based for loops (NFC)
2021-12-11 11:29:12 -08:00
AArch64ExpandImm.h
…
AArch64ExpandPseudoInsts.cpp
[ObjCARC] Require the function argument in the clang.arc.attachedcall bundle.
2022-01-28 12:41:45 -08:00
AArch64FalkorHWPFFix.cpp
[llvm] Use depth_first (NFC)
2021-12-21 22:28:48 -08:00
AArch64FastISel.cpp
[NFC] Use Register instead of unsigned
2022-01-19 20:17:04 +08:00
AArch64FrameLowering.cpp
[NFC] Use Register instead of unsigned
2022-01-19 20:17:04 +08:00
AArch64FrameLowering.h
[CodeGen] Rename emitCalleeSavedFrameMoves
2022-01-10 01:33:04 +00:00
AArch64GenRegisterBankInfo.def
…
AArch64InstrAtomics.td
[AArch64] Add patterns for relaxed atomic ld/st into fp registers
2022-01-25 15:33:37 +03:00
AArch64InstrFormats.td
[ARM][AArch64] Introduce qrdmlah and qrdmlsh intrinsics
2022-01-27 19:19:46 +00:00
AArch64InstrGISel.td
…
AArch64InstrInfo.cpp
[AArch64] Make machine combiner patterns preserve MIFlags
2022-02-03 11:58:59 +00:00
AArch64InstrInfo.h
[Target] Remove unused forward declarations (NFC)
2022-01-02 10:20:15 -08:00
AArch64InstrInfo.td
[AArch64] Expand UADDLV patterns to SADDLV
2022-02-04 14:07:02 +00:00
AArch64ISelDAGToDAG.cpp
[AArch64][SVE] Folds VSELECT if the predicate is all active.
2022-01-27 15:58:56 +00:00
AArch64ISelLowering.cpp
[NFC][SVE] Change useSVEForFixedLengthVectorVT to allow unconditional SVE usage for NEON sized vectors.
2022-02-04 14:34:35 +00:00
AArch64ISelLowering.h
[AArch64] Reassociate integer extending reductions to pairwise addition.
2022-02-03 11:05:48 +00:00
AArch64LoadStoreOptimizer.cpp
[NFC] Use Register instead of unsigned
2022-01-19 20:17:04 +08:00
AArch64LowerHomogeneousPrologEpilog.cpp
[llvm] Use llvm::is_contained (NFC)
2021-10-14 22:44:09 -07:00
AArch64MachineFunctionInfo.cpp
[llvm] Rename StringRef _lower() method calls to _insensitive()
2021-06-25 00:22:01 +03:00
AArch64MachineFunctionInfo.h
…
AArch64MacroFusion.cpp
…
AArch64MacroFusion.h
…
AArch64MCInstLower.cpp
…
AArch64MCInstLower.h
[Target] Remove unused forward declarations (NFC)
2022-01-02 10:20:15 -08:00
AArch64MIPeepholeOpt.cpp
[AArch64] Fixes ADD/SUB opt bug and abstracts shared behavior in MIPeepholeOpt for ADD, SUB, and AND.
2022-01-26 04:22:27 +00:00
AArch64PBQPRegAlloc.cpp
…
AArch64PBQPRegAlloc.h
…
AArch64PerfectShuffle.h
…
AArch64PfmCounters.td
…
AArch64PromoteConstant.cpp
…
AArch64RedundantCopyElimination.cpp
…
AArch64RegisterBanks.td
…
AArch64RegisterInfo.cpp
Reduce dependencies on llvm/BinaryFormat/Dwarf.h
2022-02-04 11:44:03 +01:00
AArch64RegisterInfo.h
…
AArch64RegisterInfo.td
[AArch64][SVE] NFC: Remove unused p0-p7 with element size predicates
2021-08-10 07:56:22 +00:00
AArch64SchedA53.td
[AArch64] Model Cortex-A55 Q register NEON instructions
2021-09-29 16:55:31 +01:00
AArch64SchedA55.td
[SchedModels][CortexA55] Fix scheduling of FP loads
2022-01-10 10:14:45 +03:00
AArch64SchedA57.td
[AArch64] Rename CPY to DUP. NFC
2022-01-05 20:02:39 +00:00
AArch64SchedA57WriteRes.td
…
AArch64SchedA64FX.td
[AArch64] Rename CPY to DUP. NFC
2022-01-05 20:02:39 +00:00
AArch64SchedCyclone.td
[AArch64] Model Cortex-A55 Q register NEON instructions
2021-09-29 16:55:31 +01:00
AArch64SchedExynosM3.td
[AArch64] Rename CPY to DUP. NFC
2022-01-05 20:02:39 +00:00
AArch64SchedExynosM4.td
[AArch64] Rename CPY to DUP. NFC
2022-01-05 20:02:39 +00:00
AArch64SchedExynosM5.td
[AArch64] Rename CPY to DUP. NFC
2022-01-05 20:02:39 +00:00
AArch64SchedFalkor.td
[AArch64] Model Cortex-A55 Q register NEON instructions
2021-09-29 16:55:31 +01:00
AArch64SchedFalkorDetails.td
[AArch64] Rename CPY to DUP. NFC
2022-01-05 20:02:39 +00:00
AArch64SchedKryo.td
[AArch64] Model Cortex-A55 Q register NEON instructions
2021-09-29 16:55:31 +01:00
AArch64SchedKryoDetails.td
…
AArch64SchedPredExynos.td
…
AArch64SchedPredicates.td
…
AArch64SchedThunderX2T99.td
[AArch64] Rename CPY to DUP. NFC
2022-01-05 20:02:39 +00:00
AArch64SchedThunderX3T110.td
[AArch64] Rename CPY to DUP. NFC
2022-01-05 20:02:39 +00:00
AArch64SchedThunderX.td
[AArch64] Model Cortex-A55 Q register NEON instructions
2021-09-29 16:55:31 +01:00
AArch64SchedTSV110.td
[AArch64] Model Cortex-A55 Q register NEON instructions
2021-09-29 16:55:31 +01:00
AArch64Schedule.td
[AArch64] Model Cortex-A55 Q register NEON instructions
2021-09-29 16:55:31 +01:00
AArch64SelectionDAGInfo.cpp
[AArch64][SelectionDAG] CodeGen for Armv8.8/9.3 MOPS
2022-01-31 20:56:27 +00:00
AArch64SelectionDAGInfo.h
[AArch64][SelectionDAG] CodeGen for Armv8.8/9.3 MOPS
2022-01-31 20:56:27 +00:00
AArch64SIMDInstrOpt.cpp
[llvm] Use nullptr instead of 0 (NFC)
2021-12-28 08:52:25 -08:00
AArch64SLSHardening.cpp
…
AArch64SMEInstrInfo.td
[AArch64][SME] Update DUP (predicate) instruction
2021-10-07 08:55:11 +00:00
AArch64SpeculationHardening.cpp
[NFC] Use Register instead of unsigned
2022-01-19 20:17:04 +08:00
AArch64StackTagging.cpp
[mte] [nfc] do not keep Tag in AllocaInfo
2022-02-04 12:34:22 -08:00
AArch64StackTaggingPreRA.cpp
[NFC] Use Register instead of unsigned
2022-01-19 20:17:04 +08:00
AArch64StorePairSuppress.cpp
[AArch64] Disable AArch64StorePairSuppress under optsize
2021-10-04 18:28:15 +01:00
AArch64Subtarget.cpp
[ARM] Add Cortex-X1C Support for Clang and LLVM
2022-01-31 14:23:35 +00:00
AArch64Subtarget.h
[AArch64] Removing redundant PAuth flag
2022-01-31 21:00:30 +00:00
AArch64SVEInstrInfo.td
[AArch64][SVE] Remove false register dependency for unary FP convert operations
2022-02-04 09:55:39 +00:00
AArch64SystemOperands.td
[AArch64] Remove PRBAR0_ELn and PRLAR0_ELn sysregs.
2022-01-20 13:37:58 +00:00
AArch64TargetMachine.cpp
[AArch64] Use Feature for A53 Erratum 835769 Fix
2021-12-10 15:09:59 +00:00
AArch64TargetMachine.h
[Target] Remove unused forward declarations (NFC)
2022-01-02 10:20:15 -08:00
AArch64TargetObjectFile.cpp
[Target] Remove redundant member initialization (NFC)
2022-01-06 22:01:44 -08:00
AArch64TargetObjectFile.h
[Target] Remove unused forward declarations (NFC)
2022-01-02 10:20:15 -08:00
AArch64TargetTransformInfo.cpp
[AArch64] Fix costs of float vector compare/selects pairs.
2022-01-31 10:18:29 +00:00
AArch64TargetTransformInfo.h
[LoopVectorize][AArch64] Use get.active.lane.mask intrinsic when SVE is enabled
2022-01-18 11:59:30 +00:00
CMakeLists.txt
Third Recommit "[AArch64] Split bitmask immediate of bitwise AND operation"
2021-10-08 11:28:49 +01:00
SMEInstrFormats.td
[AArch64][SME] Update DUP (predicate) instruction
2021-10-07 08:55:11 +00:00
SVEInstrFormats.td
[AArch64][SVE] Remove false register dependency for unary FP convert operations
2022-02-04 09:55:39 +00:00
SVEIntrinsicOpts.cpp
[Aarch64] Remove redundant declaration initializeSVEIntrinsicOptsPass (NFC)
2022-01-01 09:14:25 -08:00