7d926b7177
The new LEGALAVL node annotates that the AVL refers to packs of 64bit. We use a two-stage lowering approach with LEGALAVL: First, standard SDNodes are translated into illegal VVP layer nodes. Regardless of source (VP or standard), all VVP nodes have a mask and AVL parameter. The AVL parameter refers to the element position (just as in VP intrinsics). Second, we legalize the AVL usage in VVP layer nodes. If the element size is < 64bit, the EVL parameter has to be adjusted to refer to packs of 64bits. We wrap the legalized AVL in a LEGALAVL node to track this. Reviewed By: kaz7 Differential Revision: https://reviews.llvm.org/D118321
152 lines
4.2 KiB
C++
152 lines
4.2 KiB
C++
//===-- VECustomDAG.h - VE Custom DAG Nodes ------------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the interfaces that VE uses to lower LLVM code into a
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// selection DAG.
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//
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//===----------------------------------------------------------------------===//
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#include "VECustomDAG.h"
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#ifndef DEBUG_TYPE
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#define DEBUG_TYPE "vecustomdag"
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#endif
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namespace llvm {
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static const int StandardVectorWidth = 256;
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bool isPackedVectorType(EVT SomeVT) {
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if (!SomeVT.isVector())
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return false;
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return SomeVT.getVectorNumElements() > StandardVectorWidth;
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}
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/// \returns the VVP_* SDNode opcode corresponsing to \p OC.
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Optional<unsigned> getVVPOpcode(unsigned Opcode) {
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switch (Opcode) {
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#define HANDLE_VP_TO_VVP(VPOPC, VVPNAME) \
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case ISD::VPOPC: \
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return VEISD::VVPNAME;
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#define ADD_VVP_OP(VVPNAME, SDNAME) \
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case VEISD::VVPNAME: \
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case ISD::SDNAME: \
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return VEISD::VVPNAME;
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#include "VVPNodes.def"
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}
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return None;
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}
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bool maySafelyIgnoreMask(SDValue Op) {
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auto VVPOpc = getVVPOpcode(Op->getOpcode());
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auto Opc = VVPOpc.getValueOr(Op->getOpcode());
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switch (Opc) {
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case VEISD::VVP_SDIV:
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case VEISD::VVP_UDIV:
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case VEISD::VVP_FDIV:
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case VEISD::VVP_SELECT:
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return false;
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default:
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return true;
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}
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}
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bool isVVPOrVEC(unsigned Opcode) {
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switch (Opcode) {
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case VEISD::VEC_BROADCAST:
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#define ADD_VVP_OP(VVPNAME, ...) case VEISD::VVPNAME:
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#include "VVPNodes.def"
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return true;
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}
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return false;
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}
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bool isVVPBinaryOp(unsigned VVPOpcode) {
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switch (VVPOpcode) {
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#define ADD_BINARY_VVP_OP(VVPNAME, ...) \
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case VEISD::VVPNAME: \
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return true;
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#include "VVPNodes.def"
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}
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return false;
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}
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// Return the AVL operand position for this VVP or VEC Op.
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Optional<int> getAVLPos(unsigned Opc) {
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// This is only available for VP SDNodes
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auto PosOpt = ISD::getVPExplicitVectorLengthIdx(Opc);
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if (PosOpt)
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return *PosOpt;
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// VVP Opcodes.
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if (isVVPBinaryOp(Opc))
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return 3;
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// VM Opcodes.
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switch (Opc) {
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case VEISD::VEC_BROADCAST:
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return 1;
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case VEISD::VVP_SELECT:
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return 3;
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}
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return None;
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}
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bool isLegalAVL(SDValue AVL) { return AVL->getOpcode() == VEISD::LEGALAVL; }
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SDValue getNodeAVL(SDValue Op) {
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auto PosOpt = getAVLPos(Op->getOpcode());
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return PosOpt ? Op->getOperand(*PosOpt) : SDValue();
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}
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std::pair<SDValue, bool> getAnnotatedNodeAVL(SDValue Op) {
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SDValue AVL = getNodeAVL(Op);
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if (!AVL)
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return {SDValue(), true};
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if (isLegalAVL(AVL))
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return {AVL->getOperand(0), true};
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return {AVL, false};
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}
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SDValue VECustomDAG::getConstant(uint64_t Val, EVT VT, bool IsTarget,
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bool IsOpaque) const {
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return DAG.getConstant(Val, DL, VT, IsTarget, IsOpaque);
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}
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SDValue VECustomDAG::getBroadcast(EVT ResultVT, SDValue Scalar,
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SDValue AVL) const {
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assert(ResultVT.isVector());
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auto ScaVT = Scalar.getValueType();
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assert(ScaVT != MVT::i1 && "TODO: Mask broadcasts");
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if (isPackedVectorType(ResultVT)) {
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// v512x packed mode broadcast
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// Replicate the scalar reg (f32 or i32) onto the opposing half of the full
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// scalar register. If it's an I64 type, assume that this has already
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// happened.
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if (ScaVT == MVT::f32) {
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Scalar = getNode(VEISD::REPL_F32, MVT::i64, Scalar);
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} else if (ScaVT == MVT::i32) {
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Scalar = getNode(VEISD::REPL_I32, MVT::i64, Scalar);
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}
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}
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return getNode(VEISD::VEC_BROADCAST, ResultVT, {Scalar, AVL});
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}
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SDValue VECustomDAG::annotateLegalAVL(SDValue AVL) const {
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if (isLegalAVL(AVL))
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return AVL;
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return getNode(VEISD::LEGALAVL, AVL.getValueType(), AVL);
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}
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} // namespace llvm
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