068c2ce836
As discussed on the ml, backend tests need to be put in llvm/test/CodeGen/X86 as fast-isel tests using IR that is as close to what is generated here as possible. The llvm tests will (re)added in a future commit I will update PR24580 on this new plan llvm-svn: 254594
109 lines
3.4 KiB
C
109 lines
3.4 KiB
C
// RUN: %clang_cc1 %s -triple=x86_64-apple-darwin -target-feature +ssse3 -emit-llvm -o - -Werror | FileCheck %s
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// Don't include mm_malloc.h, it's system specific.
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#define __MM_MALLOC_H
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#include <x86intrin.h>
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__m128i test_mm_abs_epi8(__m128i a) {
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// CHECK-LABEL: test_mm_abs_epi8
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// CHECK: call <16 x i8> @llvm.x86.ssse3.pabs.b.128
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return _mm_abs_epi8(a);
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}
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__m128i test_mm_abs_epi16(__m128i a) {
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// CHECK-LABEL: test_mm_abs_epi16
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// CHECK: call <8 x i16> @llvm.x86.ssse3.pabs.w.128
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return _mm_abs_epi16(a);
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}
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__m128i test_mm_abs_epi32(__m128i a) {
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// CHECK-LABEL: test_mm_abs_epi32
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// CHECK: call <4 x i32> @llvm.x86.ssse3.pabs.d.128
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return _mm_abs_epi32(a);
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}
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__m128i test_mm_alignr_epi8(__m128i a, __m128i b) {
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// CHECK-LABEL: test_mm_alignr_epi8
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// CHECK: shufflevector <16 x i8> %{{.*}}, <16 x i8> %{{.*}}, <16 x i32> <i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17>
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return _mm_alignr_epi8(a, b, 2);
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}
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__m128i test2_mm_alignr_epi8(__m128i a, __m128i b) {
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// CHECK-LABEL: test2_mm_alignr_epi8
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// CHECK: shufflevector <16 x i8> %{{.*}}, <16 x i8> zeroinitializer, <16 x i32> <i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16>
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return _mm_alignr_epi8(a, b, 17);
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}
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__m128i test_mm_hadd_epi16(__m128i a, __m128i b) {
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// CHECK-LABEL: test_mm_hadd_epi16
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// CHECK: call <8 x i16> @llvm.x86.ssse3.phadd.w.128
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return _mm_hadd_epi16(a, b);
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}
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__m128i test_mm_hadd_epi32(__m128i a, __m128i b) {
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// CHECK-LABEL: test_mm_hadd_epi32
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// CHECK: call <4 x i32> @llvm.x86.ssse3.phadd.d.128
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return _mm_hadd_epi32(a, b);
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}
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__m128i test_mm_hadds_epi16(__m128i a, __m128i b) {
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// CHECK-LABEL: test_mm_hadds_epi16
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// CHECK: call <8 x i16> @llvm.x86.ssse3.phadd.sw.128
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return _mm_hadds_epi16(a, b);
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}
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__m128i test_mm_hsub_epi16(__m128i a, __m128i b) {
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// CHECK-LABEL: test_mm_hsub_epi16
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// CHECK: call <8 x i16> @llvm.x86.ssse3.phsub.w.128
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return _mm_hsub_epi16(a, b);
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}
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__m128i test_mm_hsub_epi32(__m128i a, __m128i b) {
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// CHECK-LABEL: test_mm_hsub_epi32
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// CHECK: call <4 x i32> @llvm.x86.ssse3.phsub.d.128
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return _mm_hsub_epi32(a, b);
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}
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__m128i test_mm_hsubs_epi16(__m128i a, __m128i b) {
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// CHECK-LABEL: test_mm_hsubs_epi16
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// CHECK: call <8 x i16> @llvm.x86.ssse3.phsub.sw.128
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return _mm_hsubs_epi16(a, b);
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}
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__m128i test_mm_maddubs_epi16(__m128i a, __m128i b) {
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// CHECK-LABEL: test_mm_maddubs_epi16
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// CHECK: call <8 x i16> @llvm.x86.ssse3.pmadd.ub.sw.128
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return _mm_maddubs_epi16(a, b);
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}
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__m128i test_mm_mulhrs_epi16(__m128i a, __m128i b) {
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// CHECK-LABEL: test_mm_mulhrs_epi16
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// CHECK: call <8 x i16> @llvm.x86.ssse3.pmul.hr.sw.128
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return _mm_mulhrs_epi16(a, b);
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}
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__m128i test_mm_shuffle_epi8(__m128i a, __m128i b) {
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// CHECK-LABEL: test_mm_shuffle_epi8
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// CHECK: call <16 x i8> @llvm.x86.ssse3.pshuf.b.128
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return _mm_shuffle_epi8(a, b);
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}
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__m128i test_mm_sign_epi8(__m128i a, __m128i b) {
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// CHECK-LABEL: test_mm_sign_epi8
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// CHECK: call <16 x i8> @llvm.x86.ssse3.psign.b.128
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return _mm_sign_epi8(a, b);
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}
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__m128i test_mm_sign_epi16(__m128i a, __m128i b) {
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// CHECK-LABEL: test_mm_sign_epi16
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// CHECK: call <8 x i16> @llvm.x86.ssse3.psign.w.128
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return _mm_sign_epi16(a, b);
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}
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__m128i test_mm_sign_epi32(__m128i a, __m128i b) {
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// CHECK-LABEL: test_mm_sign_epi32
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// CHECK: call <4 x i32> @llvm.x86.ssse3.psign.d.128
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return _mm_sign_epi32(a, b);
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}
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