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llvm-project/llvm/test/CodeGen/SPARC
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Koakuma 2ef0104862
[SPARC] Use native bitcast instructions when we have VIS3 
Reviewers: brad0, s-barannikov, rorth

Reviewed By: s-barannikov

Pull Request: https://github.com/llvm/llvm-project/pull/135716
2025-04-17 23:39:46 +07:00
..
32abi.ll
[RegAlloc] Sort CopyHint by IsCSR (#131046)
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64abi.ll
[RegAlloc] Sort CopyHint by IsCSR (#131046)
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64atomics.ll
[Sparc,test] Change llc -march= to -mtriple=
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64bit.ll
[Sparc,test] Change llc -march= to -mtriple=
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64cond.ll
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64spill.ll
[Sparc,test] Change llc -march= to -mtriple=
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2006-01-22-BitConvertLegalize.ll
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2007-05-09-JumpTables.ll
[Sparc,test] Change llc -march= to -mtriple=
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2007-07-05-LiveIntervalAssert.ll
[Sparc,test] Change llc -march= to -mtriple=
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2008-10-10-InlineAsmMemoryOperand.ll
[Sparc,test] Change llc -march= to -mtriple=
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2008-10-10-InlineAsmRegOperand.ll
[Sparc,test] Change llc -march= to -mtriple=
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2009-08-28-PIC.ll
[Sparc,test] Change llc -march= to -mtriple=
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2009-08-28-WeakLinkage.ll
[Sparc,test] Change llc -march= to -mtriple=
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2011-01-11-Call.ll
[Sparc,test] Change llc -march= to -mtriple=
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2011-01-11-CC.ll
[SPARC] Use addxccc to do multiword addition when we have VIS3
2025-04-16 08:36:47 +07:00
2011-01-11-FrameAddr.ll
[Sparc,test] Change llc -march= to -mtriple=
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2011-01-19-DelaySlot.ll
[RegAlloc] Sort CopyHint by IsCSR (#131046)
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2011-01-21-ByValArgs.ll
[Sparc,test] Change llc -march= to -mtriple=
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2011-01-22-SRet.ll
[Sparc,test] Change llc -march= to -mtriple=
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2011-12-03-TailDuplication.ll
[Sparc,test] Change llc -march= to -mtriple=
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2012-05-01-LowerArguments.ll
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2013-05-17-CallFrame.ll
[Sparc,test] Change llc -march= to -mtriple=
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alloca-align.ll
[Sparc,test] Change llc -march= to -mtriple=
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analyze-branch.ll
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atomicrmw-uinc-udec-wrap.ll
[Sparc,test] Change llc -march= to -mtriple=
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atomics.ll
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basictest.ll
[Sparc,test] Change llc -march= to -mtriple=
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bigreturn.ll
[RegAlloc] Sort CopyHint by IsCSR (#131046)
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bitcast.ll
[SPARC] Use native bitcast instructions when we have VIS3
2025-04-17 23:39:46 +07:00
blockaddr.ll
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branches-relax.ll
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branches-v9.ll
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cast-sret-func.ll
[Sparc,test] Change llc -march= to -mtriple=
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codemodel.ll
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constpool.ll
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constructor.ll
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ctlz.ll
[SPARC] Use lzcnt to implement CTLZ when we have VIS3
2025-04-17 23:37:00 +07:00
ctpop.ll
[Sparc,test] Change llc -march= to -mtriple=
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cttz.ll
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data-align.ll
[Sparc,test] Change llc -march= to -mtriple=
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DbgValueOtherTargets.test
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disable-fsmuld-fmuls.ll
[Sparc,test] Change llc -march= to -mtriple=
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empty-functions.ll
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exception.ll
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float-constants.ll
[SPARC] Use fzero/fzeros to materialize FP zeros when we have VIS
2025-04-16 08:33:42 +07:00
float.ll
[Sparc,test] Change llc -march= to -mtriple=
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fmuladd-soft-float.ll
[RegAlloc] Sort CopyHint by IsCSR (#131046)
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fp16-promote.ll
[CodeGen] Use __extendhfsf2 and __truncsfhf2 by default (#126880)
2025-02-19 10:16:57 +01:00
fp128-select.ll
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fp128-split.ll
DAG: Preserve disjoint flag when emitting final instructions (#110795)
2024-10-02 19:37:04 +04:00
fp128.ll
PeepholeOpt: Fix looking for def of current copy to coalesce (#125533)
2025-02-05 23:29:02 +07:00
fshl.ll
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func-addr.ll
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getpcx-call.ll
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getpcx-rdpc.ll
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globals.ll
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hard-quad-float.ll
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imm.ll
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inline-asm-i-constraint-i1.ll
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inlineasm-bad.ll
[Sparc,test] Change llc -march= to -mtriple=
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inlineasm-output-template.ll
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inlineasm-v9.ll
[Sparc,test] Change llc -march= to -mtriple=
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inlineasm.ll
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leafproc.ll
[RegAlloc] Sort CopyHint by IsCSR (#131046)
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LeonCASAInstructionUT.ll
[Sparc,test] Change llc -march= to -mtriple=
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LeonDetectRoundChangePassUT.ll
[Sparc,test] Change llc -march= to -mtriple=
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LeonFixAllFDIVSQRTPassUT.ll
[Sparc,test] Change llc -march= to -mtriple=
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LeonInsertNOPLoadPassUT.ll
[Sparc,test] Change llc -march= to -mtriple=
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LeonItinerariesUT.ll
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LeonSMACUMACInstructionUT.ll
[Sparc,test] Change llc -march= to -mtriple=
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lit.local.cfg
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mature-mc-support.ll
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missing-sret.ll
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missinglabel.ll
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mult-alt-generic-sparc.ll
[Sparc,test] Change llc -march= to -mtriple=
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multiple-div.ll
[Sparc,test] Change llc -march= to -mtriple=
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naked-fn-with-frame-pointer.ll
[llvm] Consistently respect naked fn attribute in TargetFrameLowering::hasFP() (#106014)
2024-10-18 09:35:42 +04:00
obj-relocs.ll
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overflow-intrinsic-optimizations.ll
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parts.ll
[RegAlloc] Sort CopyHint by IsCSR (#131046)
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pic.ll
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private.ll
[Sparc,test] Change llc -march= to -mtriple=
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readcycle.ll
[Sparc,test] Change llc -march= to -mtriple=
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reg64.ll
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register-clobber.ll
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rem.ll
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reserved-arg-regs.ll
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reserved-regs-named.ll
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reserved-regs-unavailable.ll
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reserved-regs.ll
[Sparc,test] Change llc -march= to -mtriple=
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salvage-debug-isel.ll
[Sparc,test] Change llc -march= to -mtriple=
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select-mask.ll
[Sparc,test] Change llc -march= to -mtriple=
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sethiandn.ll
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setjmp.ll
[Sparc,test] Change llc -march= to -mtriple=
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smulo-128-legalisation-lowering.ll
Revert "[SPARC] Use umulxhi to do extending 64x64->128 multiply when we have VIS3" (#135897)
2025-04-16 09:27:17 +07:00
soft-float.ll
[Sparc,test] Change llc -march= to -mtriple=
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soft-mul-div.ll
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spill.ll
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spillsize.ll
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sret-secondary.ll
[Sparc,test] Change llc -march= to -mtriple=
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stack-align.ll
[Sparc,test] Change llc -march= to -mtriple=
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stack-protector.ll
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tailcall.ll
[RegAlloc] Sort CopyHint by IsCSR (#131046)
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thread-pointer.ll
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tls.ll
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tn0009.mir
[Sparc,test] Change llc -march= to -mtriple=
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tn0010.mir
[Sparc,test] Change llc -march= to -mtriple=
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tn0011.ll
[Sparc] Add errata workaround pass for GR712RC and UT700 (#103843)
2024-08-19 07:59:58 +02:00
tn0012.mir
[Sparc,test] Change llc -march= to -mtriple=
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tn0013.mir
[Sparc,test] Change llc -march= to -mtriple=
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trap.ll
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umulo-128-legalisation-lowering.ll
Revert "[SPARC] Use umulxhi to do extending 64x64->128 multiply when we have VIS3" (#135897)
2025-04-16 09:27:17 +07:00
varargs-v8.ll
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varargs.ll
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vector-call.ll
[Sparc,test] Change llc -march= to -mtriple=
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vector-extract-elt.ll
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zerostructcall.ll
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