2946cd7010
to reflect the new license. We understand that people may be surprised that we're moving the header entirely to discuss the new license. We checked this carefully with the Foundation's lawyer and we believe this is the correct approach. Essentially, all code in the project is now made available by the LLVM project under our new license, so you will see that the license headers include that license only. Some of our contributors have contributed code under our old license, and accordingly, we have retained a copy of our old license notice in the top-level files in each project and repository. llvm-svn: 351636
335 lines
14 KiB
C++
335 lines
14 KiB
C++
//===-- lib/CodeGen/GlobalISel/GICombinerHelper.cpp -----------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/CodeGen/GlobalISel/CombinerHelper.h"
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#include "llvm/CodeGen/GlobalISel/Combiner.h"
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#include "llvm/CodeGen/GlobalISel/GISelChangeObserver.h"
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#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
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#include "llvm/CodeGen/GlobalISel/Utils.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/TargetInstrInfo.h"
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#define DEBUG_TYPE "gi-combiner"
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using namespace llvm;
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CombinerHelper::CombinerHelper(GISelChangeObserver &Observer,
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MachineIRBuilder &B)
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: Builder(B), MRI(Builder.getMF().getRegInfo()), Observer(Observer) {}
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void CombinerHelper::replaceRegWith(MachineRegisterInfo &MRI, unsigned FromReg,
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unsigned ToReg) const {
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Observer.changingAllUsesOfReg(MRI, FromReg);
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if (MRI.constrainRegAttrs(ToReg, FromReg))
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MRI.replaceRegWith(FromReg, ToReg);
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else
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Builder.buildCopy(ToReg, FromReg);
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Observer.finishedChangingAllUsesOfReg();
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}
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void CombinerHelper::replaceRegOpWith(MachineRegisterInfo &MRI,
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MachineOperand &FromRegOp,
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unsigned ToReg) const {
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assert(FromRegOp.getParent() && "Expected an operand in an MI");
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Observer.changingInstr(*FromRegOp.getParent());
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FromRegOp.setReg(ToReg);
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Observer.changedInstr(*FromRegOp.getParent());
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}
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bool CombinerHelper::tryCombineCopy(MachineInstr &MI) {
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if (MI.getOpcode() != TargetOpcode::COPY)
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return false;
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unsigned DstReg = MI.getOperand(0).getReg();
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unsigned SrcReg = MI.getOperand(1).getReg();
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LLT DstTy = MRI.getType(DstReg);
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LLT SrcTy = MRI.getType(SrcReg);
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// Simple Copy Propagation.
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// a(sx) = COPY b(sx) -> Replace all uses of a with b.
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if (DstTy.isValid() && SrcTy.isValid() && DstTy == SrcTy) {
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MI.eraseFromParent();
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replaceRegWith(MRI, DstReg, SrcReg);
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return true;
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}
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return false;
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}
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namespace {
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struct PreferredTuple {
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LLT Ty; // The result type of the extend.
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unsigned ExtendOpcode; // G_ANYEXT/G_SEXT/G_ZEXT
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MachineInstr *MI;
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};
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/// Select a preference between two uses. CurrentUse is the current preference
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/// while *ForCandidate is attributes of the candidate under consideration.
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PreferredTuple ChoosePreferredUse(PreferredTuple &CurrentUse,
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const LLT &TyForCandidate,
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unsigned OpcodeForCandidate,
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MachineInstr *MIForCandidate) {
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if (!CurrentUse.Ty.isValid()) {
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if (CurrentUse.ExtendOpcode == OpcodeForCandidate ||
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CurrentUse.ExtendOpcode == TargetOpcode::G_ANYEXT)
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return {TyForCandidate, OpcodeForCandidate, MIForCandidate};
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return CurrentUse;
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}
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// We permit the extend to hoist through basic blocks but this is only
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// sensible if the target has extending loads. If you end up lowering back
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// into a load and extend during the legalizer then the end result is
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// hoisting the extend up to the load.
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// Prefer defined extensions to undefined extensions as these are more
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// likely to reduce the number of instructions.
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if (OpcodeForCandidate == TargetOpcode::G_ANYEXT &&
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CurrentUse.ExtendOpcode != TargetOpcode::G_ANYEXT)
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return CurrentUse;
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else if (CurrentUse.ExtendOpcode == TargetOpcode::G_ANYEXT &&
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OpcodeForCandidate != TargetOpcode::G_ANYEXT)
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return {TyForCandidate, OpcodeForCandidate, MIForCandidate};
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// Prefer sign extensions to zero extensions as sign-extensions tend to be
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// more expensive.
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if (CurrentUse.Ty == TyForCandidate) {
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if (CurrentUse.ExtendOpcode == TargetOpcode::G_SEXT &&
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OpcodeForCandidate == TargetOpcode::G_ZEXT)
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return CurrentUse;
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else if (CurrentUse.ExtendOpcode == TargetOpcode::G_ZEXT &&
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OpcodeForCandidate == TargetOpcode::G_SEXT)
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return {TyForCandidate, OpcodeForCandidate, MIForCandidate};
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}
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// This is potentially target specific. We've chosen the largest type
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// because G_TRUNC is usually free. One potential catch with this is that
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// some targets have a reduced number of larger registers than smaller
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// registers and this choice potentially increases the live-range for the
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// larger value.
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if (TyForCandidate.getSizeInBits() > CurrentUse.Ty.getSizeInBits()) {
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return {TyForCandidate, OpcodeForCandidate, MIForCandidate};
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}
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return CurrentUse;
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}
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/// Find a suitable place to insert some instructions and insert them. This
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/// function accounts for special cases like inserting before a PHI node.
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/// The current strategy for inserting before PHI's is to duplicate the
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/// instructions for each predecessor. However, while that's ok for G_TRUNC
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/// on most targets since it generally requires no code, other targets/cases may
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/// want to try harder to find a dominating block.
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static void InsertInsnsWithoutSideEffectsBeforeUse(
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MachineIRBuilder &Builder, MachineInstr &DefMI, MachineOperand &UseMO,
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std::function<void(MachineBasicBlock *, MachineBasicBlock::iterator)>
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Inserter) {
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MachineInstr &UseMI = *UseMO.getParent();
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MachineBasicBlock *InsertBB = UseMI.getParent();
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// If the use is a PHI then we want the predecessor block instead.
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if (UseMI.isPHI()) {
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MachineOperand *PredBB = std::next(&UseMO);
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InsertBB = PredBB->getMBB();
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}
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// If the block is the same block as the def then we want to insert just after
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// the def instead of at the start of the block.
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if (InsertBB == DefMI.getParent()) {
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MachineBasicBlock::iterator InsertPt = &DefMI;
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Inserter(InsertBB, std::next(InsertPt));
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return;
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}
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// Otherwise we want the start of the BB
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Inserter(InsertBB, InsertBB->getFirstNonPHI());
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}
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} // end anonymous namespace
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bool CombinerHelper::tryCombineExtendingLoads(MachineInstr &MI) {
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struct InsertionPoint {
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MachineOperand *UseMO;
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MachineBasicBlock *InsertIntoBB;
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MachineBasicBlock::iterator InsertBefore;
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InsertionPoint(MachineOperand *UseMO, MachineBasicBlock *InsertIntoBB,
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MachineBasicBlock::iterator InsertBefore)
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: UseMO(UseMO), InsertIntoBB(InsertIntoBB), InsertBefore(InsertBefore) {
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}
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};
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// We match the loads and follow the uses to the extend instead of matching
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// the extends and following the def to the load. This is because the load
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// must remain in the same position for correctness (unless we also add code
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// to find a safe place to sink it) whereas the extend is freely movable.
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// It also prevents us from duplicating the load for the volatile case or just
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// for performance.
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if (MI.getOpcode() != TargetOpcode::G_LOAD &&
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MI.getOpcode() != TargetOpcode::G_SEXTLOAD &&
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MI.getOpcode() != TargetOpcode::G_ZEXTLOAD)
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return false;
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auto &LoadValue = MI.getOperand(0);
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assert(LoadValue.isReg() && "Result wasn't a register?");
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LLT LoadValueTy = MRI.getType(LoadValue.getReg());
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if (!LoadValueTy.isScalar())
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return false;
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// Find the preferred type aside from the any-extends (unless it's the only
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// one) and non-extending ops. We'll emit an extending load to that type and
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// and emit a variant of (extend (trunc X)) for the others according to the
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// relative type sizes. At the same time, pick an extend to use based on the
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// extend involved in the chosen type.
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unsigned PreferredOpcode = MI.getOpcode() == TargetOpcode::G_LOAD
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? TargetOpcode::G_ANYEXT
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: MI.getOpcode() == TargetOpcode::G_SEXTLOAD
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? TargetOpcode::G_SEXT
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: TargetOpcode::G_ZEXT;
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PreferredTuple Preferred = {LLT(), PreferredOpcode, nullptr};
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for (auto &UseMI : MRI.use_instructions(LoadValue.getReg())) {
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if (UseMI.getOpcode() == TargetOpcode::G_SEXT ||
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UseMI.getOpcode() == TargetOpcode::G_ZEXT ||
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UseMI.getOpcode() == TargetOpcode::G_ANYEXT) {
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Preferred = ChoosePreferredUse(Preferred,
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MRI.getType(UseMI.getOperand(0).getReg()),
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UseMI.getOpcode(), &UseMI);
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}
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}
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// There were no extends
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if (!Preferred.MI)
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return false;
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// It should be impossible to chose an extend without selecting a different
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// type since by definition the result of an extend is larger.
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assert(Preferred.Ty != LoadValueTy && "Extending to same type?");
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LLVM_DEBUG(dbgs() << "Preferred use is: " << *Preferred.MI);
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// Rewrite the load to the chosen extending load.
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unsigned ChosenDstReg = Preferred.MI->getOperand(0).getReg();
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Observer.changingInstr(MI);
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MI.setDesc(
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Builder.getTII().get(Preferred.ExtendOpcode == TargetOpcode::G_SEXT
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? TargetOpcode::G_SEXTLOAD
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: Preferred.ExtendOpcode == TargetOpcode::G_ZEXT
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? TargetOpcode::G_ZEXTLOAD
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: TargetOpcode::G_LOAD));
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// Rewrite all the uses to fix up the types.
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SmallVector<MachineInstr *, 1> ScheduleForErase;
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SmallVector<InsertionPoint, 4> ScheduleForInsert;
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for (auto &UseMO : MRI.use_operands(LoadValue.getReg())) {
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MachineInstr *UseMI = UseMO.getParent();
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// If the extend is compatible with the preferred extend then we should fix
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// up the type and extend so that it uses the preferred use.
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if (UseMI->getOpcode() == Preferred.ExtendOpcode ||
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UseMI->getOpcode() == TargetOpcode::G_ANYEXT) {
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unsigned UseDstReg = UseMI->getOperand(0).getReg();
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MachineOperand &UseSrcMO = UseMI->getOperand(1);
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const LLT &UseDstTy = MRI.getType(UseDstReg);
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if (UseDstReg != ChosenDstReg) {
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if (Preferred.Ty == UseDstTy) {
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// If the use has the same type as the preferred use, then merge
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// the vregs and erase the extend. For example:
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// %1:_(s8) = G_LOAD ...
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// %2:_(s32) = G_SEXT %1(s8)
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// %3:_(s32) = G_ANYEXT %1(s8)
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// ... = ... %3(s32)
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// rewrites to:
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// %2:_(s32) = G_SEXTLOAD ...
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// ... = ... %2(s32)
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replaceRegWith(MRI, UseDstReg, ChosenDstReg);
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ScheduleForErase.push_back(UseMO.getParent());
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} else if (Preferred.Ty.getSizeInBits() < UseDstTy.getSizeInBits()) {
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// If the preferred size is smaller, then keep the extend but extend
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// from the result of the extending load. For example:
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// %1:_(s8) = G_LOAD ...
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// %2:_(s32) = G_SEXT %1(s8)
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// %3:_(s64) = G_ANYEXT %1(s8)
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// ... = ... %3(s64)
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/// rewrites to:
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// %2:_(s32) = G_SEXTLOAD ...
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// %3:_(s64) = G_ANYEXT %2:_(s32)
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// ... = ... %3(s64)
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replaceRegOpWith(MRI, UseSrcMO, ChosenDstReg);
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} else {
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// If the preferred size is large, then insert a truncate. For
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// example:
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// %1:_(s8) = G_LOAD ...
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// %2:_(s64) = G_SEXT %1(s8)
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// %3:_(s32) = G_ZEXT %1(s8)
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// ... = ... %3(s32)
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/// rewrites to:
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// %2:_(s64) = G_SEXTLOAD ...
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// %4:_(s8) = G_TRUNC %2:_(s32)
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// %3:_(s64) = G_ZEXT %2:_(s8)
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// ... = ... %3(s64)
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InsertInsnsWithoutSideEffectsBeforeUse(
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Builder, MI, UseMO,
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[&](MachineBasicBlock *InsertIntoBB,
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MachineBasicBlock::iterator InsertBefore) {
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ScheduleForInsert.emplace_back(&UseMO, InsertIntoBB, InsertBefore);
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});
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}
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continue;
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}
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// The use is (one of) the uses of the preferred use we chose earlier.
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// We're going to update the load to def this value later so just erase
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// the old extend.
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ScheduleForErase.push_back(UseMO.getParent());
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continue;
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}
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// The use isn't an extend. Truncate back to the type we originally loaded.
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// This is free on many targets.
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InsertInsnsWithoutSideEffectsBeforeUse(
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Builder, MI, UseMO,
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[&](MachineBasicBlock *InsertIntoBB,
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MachineBasicBlock::iterator InsertBefore) {
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ScheduleForInsert.emplace_back(&UseMO, InsertIntoBB, InsertBefore);
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});
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}
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DenseMap<MachineBasicBlock *, MachineInstr *> EmittedInsns;
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for (auto &InsertionInfo : ScheduleForInsert) {
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MachineOperand *UseMO = InsertionInfo.UseMO;
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MachineBasicBlock *InsertIntoBB = InsertionInfo.InsertIntoBB;
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MachineBasicBlock::iterator InsertBefore = InsertionInfo.InsertBefore;
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MachineInstr *PreviouslyEmitted = EmittedInsns.lookup(InsertIntoBB);
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if (PreviouslyEmitted) {
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Observer.changingInstr(*UseMO->getParent());
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UseMO->setReg(PreviouslyEmitted->getOperand(0).getReg());
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Observer.changedInstr(*UseMO->getParent());
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continue;
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}
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Builder.setInsertPt(*InsertIntoBB, InsertBefore);
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unsigned NewDstReg = MRI.cloneVirtualRegister(MI.getOperand(0).getReg());
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MachineInstr *NewMI = Builder.buildTrunc(NewDstReg, ChosenDstReg);
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EmittedInsns[InsertIntoBB] = NewMI;
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replaceRegOpWith(MRI, *UseMO, NewDstReg);
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}
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for (auto &EraseMI : ScheduleForErase) {
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Observer.erasingInstr(*EraseMI);
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EraseMI->eraseFromParent();
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}
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MI.getOperand(0).setReg(ChosenDstReg);
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Observer.changedInstr(MI);
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return true;
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}
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bool CombinerHelper::tryCombine(MachineInstr &MI) {
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if (tryCombineCopy(MI))
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return true;
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return tryCombineExtendingLoads(MI);
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}
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