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to reflect the new license. We understand that people may be surprised that we're moving the header entirely to discuss the new license. We checked this carefully with the Foundation's lawyer and we believe this is the correct approach. Essentially, all code in the project is now made available by the LLVM project under our new license, so you will see that the license headers include that license only. Some of our contributors have contributed code under our old license, and accordingly, we have retained a copy of our old license notice in the top-level files in each project and repository. llvm-svn: 351636
108 lines
3.9 KiB
C++
108 lines
3.9 KiB
C++
//===--- WebAssemblyOptimizeLiveIntervals.cpp - LiveInterval processing ---===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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///
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/// \file
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/// Optimize LiveIntervals for use in a post-RA context.
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//
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/// LiveIntervals normally runs before register allocation when the code is
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/// only recently lowered out of SSA form, so it's uncommon for registers to
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/// have multiple defs, and when they do, the defs are usually closely related.
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/// Later, after coalescing, tail duplication, and other optimizations, it's
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/// more common to see registers with multiple unrelated defs. This pass
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/// updates LiveIntervals to distribute the value numbers across separate
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/// LiveIntervals.
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///
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//===----------------------------------------------------------------------===//
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#include "WebAssembly.h"
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#include "WebAssemblySubtarget.h"
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#include "llvm/CodeGen/LiveIntervals.h"
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#include "llvm/CodeGen/MachineBlockFrequencyInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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#define DEBUG_TYPE "wasm-optimize-live-intervals"
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namespace {
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class WebAssemblyOptimizeLiveIntervals final : public MachineFunctionPass {
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StringRef getPassName() const override {
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return "WebAssembly Optimize Live Intervals";
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}
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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AU.setPreservesCFG();
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AU.addRequired<LiveIntervals>();
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AU.addPreserved<MachineBlockFrequencyInfo>();
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AU.addPreserved<SlotIndexes>();
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AU.addPreserved<LiveIntervals>();
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AU.addPreservedID(LiveVariablesID);
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AU.addPreservedID(MachineDominatorsID);
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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bool runOnMachineFunction(MachineFunction &MF) override;
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public:
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static char ID; // Pass identification, replacement for typeid
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WebAssemblyOptimizeLiveIntervals() : MachineFunctionPass(ID) {}
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};
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} // end anonymous namespace
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char WebAssemblyOptimizeLiveIntervals::ID = 0;
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INITIALIZE_PASS(WebAssemblyOptimizeLiveIntervals, DEBUG_TYPE,
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"Optimize LiveIntervals for WebAssembly", false, false)
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FunctionPass *llvm::createWebAssemblyOptimizeLiveIntervals() {
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return new WebAssemblyOptimizeLiveIntervals();
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}
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bool WebAssemblyOptimizeLiveIntervals::runOnMachineFunction(
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MachineFunction &MF) {
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LLVM_DEBUG(dbgs() << "********** Optimize LiveIntervals **********\n"
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"********** Function: "
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<< MF.getName() << '\n');
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MachineRegisterInfo &MRI = MF.getRegInfo();
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LiveIntervals &LIS = getAnalysis<LiveIntervals>();
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// We don't preserve SSA form.
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MRI.leaveSSA();
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assert(MRI.tracksLiveness() && "OptimizeLiveIntervals expects liveness");
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// Split multiple-VN LiveIntervals into multiple LiveIntervals.
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SmallVector<LiveInterval *, 4> SplitLIs;
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for (unsigned i = 0, e = MRI.getNumVirtRegs(); i < e; ++i) {
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unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
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if (MRI.reg_nodbg_empty(Reg))
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continue;
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LIS.splitSeparateComponents(LIS.getInterval(Reg), SplitLIs);
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SplitLIs.clear();
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}
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// In PrepareForLiveIntervals, we conservatively inserted IMPLICIT_DEF
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// instructions to satisfy LiveIntervals' requirement that all uses be
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// dominated by defs. Now that LiveIntervals has computed which of these
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// defs are actually needed and which are dead, remove the dead ones.
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for (auto MII = MF.begin()->begin(), MIE = MF.begin()->end(); MII != MIE;) {
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MachineInstr *MI = &*MII++;
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if (MI->isImplicitDef() && MI->getOperand(0).isDead()) {
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LiveInterval &LI = LIS.getInterval(MI->getOperand(0).getReg());
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LIS.removeVRegDefAt(LI, LIS.getInstructionIndex(*MI).getRegSlot());
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LIS.RemoveMachineInstrFromMaps(*MI);
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MI->eraseFromParent();
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}
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}
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return false;
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}
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