Simon Pilgrim 44eb037da0
[X86] Improve handling of i512 SRL(SIGN_BIT, Amt) (#185896)
Similar to what we already do for SHL(1, Amt) - just insert the (locally
shifted) bit into a zero vector in the correct element

After this I just need to handle SRA(SIGN_BIT, Amt) and SHL/SRL(-1, Amt)
mask creation patterns and I think that's it for #132601
2026-03-12 08:40:49 +00:00
..

The LLVM Compiler Infrastructure
================================

This directory and its subdirectories contain source code for LLVM,
a toolkit for the construction of highly optimized compilers,
optimizers, and runtime environments.

LLVM is open source software. You may freely distribute it under the terms of
the license agreement found in LICENSE.txt.

Please see the documentation provided in docs/ for further
assistance with LLVM, and in particular docs/GettingStarted.rst for getting
started with LLVM and docs/README.txt for an overview of LLVM's
documentation setup.

If you are writing a package for LLVM, see docs/Packaging.rst for our
suggestions.