llvm-project

AsmParser

[AMDGPU][MC] Added lds support for MUBUF instructions

2018-02-21 13:13:48 +00:00

Disassembler

[AMDGPU][MC] Corrected dst/data size for MIMG opcodes with d16 modifier

2018-02-05 14:18:53 +00:00

InstPrinter

[AMDGPU] Add HW_REG_SH_MEM_BASES symbolic name for s_getreg_b32

2018-01-15 18:49:15 +00:00

MCTargetDesc

AMDGPU: Remove unused private member of AMDGPUTargetELFStreamer

2018-02-16 23:04:11 +00:00

TargetInfo

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Utils

AMDGPU: Bring processors and features in sync with the spec

2018-02-16 21:26:25 +00:00

AMDGPU.h

[AMDGPU] Change constant addr space to 4

2018-02-13 18:00:25 +00:00

AMDGPU.td

[MachineOperand][Target] MachineOperand::isRenamable semantics changes

2018-02-23 18:25:08 +00:00

AMDGPUAliasAnalysis.cpp

[AMDGPU] Change constant addr space to 4

2018-02-13 18:00:25 +00:00

AMDGPUAliasAnalysis.h

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AMDGPUAlwaysInlinePass.cpp

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AMDGPUAnnotateKernelFeatures.cpp

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AMDGPUAnnotateUniformValues.cpp

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AMDGPUArgumentUsageInfo.cpp

[CodeGen] Rename functions PrintReg* to printReg*

2017-11-28 12:42:37 +00:00

AMDGPUArgumentUsageInfo.h

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AMDGPUAsmPrinter.cpp

[AMDGPU] do not generate .AMDGPU.config for amdpal os type

2018-02-06 13:39:38 +00:00

AMDGPUAsmPrinter.h

[AMDGPU] add labels to +DumpCode output

2017-12-08 14:09:34 +00:00

AMDGPUCallingConv.td

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AMDGPUCallLowering.cpp

[AMDGPU] Change constant addr space to 4

2018-02-13 18:00:25 +00:00

AMDGPUCallLowering.h

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AMDGPUCodeGenPrepare.cpp

Reapply "AMDGPU: Add 32-bit constant address space"

2018-02-09 16:57:57 +00:00

AMDGPUFrameLowering.cpp

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AMDGPUFrameLowering.h

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AMDGPUGenRegisterBankInfo.def

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AMDGPUInline.cpp

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AMDGPUInstrInfo.cpp

Reapply "AMDGPU: Add 32-bit constant address space"

2018-02-09 16:57:57 +00:00

AMDGPUInstrInfo.h

AMDGPU: Fix layering issue

2018-02-09 16:57:48 +00:00

AMDGPUInstrInfo.td

AMDGPU: Add intrinsics llvm.amdgcn.cvt.{pknorm.i16, pknorm.u16, pk.i16, pk.u16}

2018-01-31 20:18:04 +00:00

AMDGPUInstructions.td

AMDGPU: Select BFI patterns with 64-bit ints

2018-02-07 00:21:34 +00:00

AMDGPUInstructionSelector.cpp

Reapply "AMDGPU: Add 32-bit constant address space"

2018-02-09 16:57:57 +00:00

AMDGPUInstructionSelector.h

[globalisel][tablegen] Generate rule coverage and use it to identify untested rules

2017-11-16 00:46:35 +00:00

AMDGPUIntrinsicInfo.cpp

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AMDGPUIntrinsicInfo.h

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AMDGPUIntrinsics.td

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AMDGPUISelDAGToDAG.cpp

Reapply "AMDGPU: Add 32-bit constant address space"

2018-02-09 16:57:57 +00:00

AMDGPUISelLowering.cpp

AMDGPU: Add intrinsics llvm.amdgcn.cvt.{pknorm.i16, pknorm.u16, pk.i16, pk.u16}

2018-01-31 20:18:04 +00:00

AMDGPUISelLowering.h

AMDGPU: Add intrinsics llvm.amdgcn.cvt.{pknorm.i16, pknorm.u16, pk.i16, pk.u16}

2018-01-31 20:18:04 +00:00

AMDGPULegalizerInfo.cpp

AMDGPU/GlobalISel: Make f64 constants legal

2018-02-26 17:20:43 +00:00

AMDGPULegalizerInfo.h

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AMDGPULibCalls.cpp

Make helpers static. NFC.

2017-11-24 14:55:41 +00:00

AMDGPULibFunc.cpp

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AMDGPULibFunc.h

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AMDGPULowerIntrinsics.cpp

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AMDGPUMachineCFGStructurizer.cpp

[CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register.

2017-12-07 10:40:31 +00:00

AMDGPUMachineFunction.cpp

MachineFunction: Return reference from getFunction(); NFC

2017-12-15 22:22:58 +00:00

AMDGPUMachineFunction.h

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AMDGPUMachineModuleInfo.cpp

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AMDGPUMachineModuleInfo.h

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AMDGPUMacroFusion.cpp

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AMDGPUMacroFusion.h

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AMDGPUMCInstLower.cpp

MachineFunction: Return reference from getFunction(); NFC

2017-12-15 22:22:58 +00:00

AMDGPUMCInstLower.h

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AMDGPUOpenCLEnqueuedBlockLowering.cpp

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AMDGPUOpenCLImageTypeLoweringPass.cpp

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AMDGPUPromoteAlloca.cpp

AMDGPU/SI: Extend promoting alloca to vector to arrays of up to 16 elements

2018-02-16 19:14:17 +00:00

AMDGPUPTNote.h

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AMDGPURegAsmNames.inc.cpp

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AMDGPURegisterBankInfo.cpp

AMDGPU: Fix layering issue

2018-02-09 16:57:48 +00:00

AMDGPURegisterBankInfo.h

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AMDGPURegisterBanks.td

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AMDGPURegisterInfo.cpp

[AMDGPU] Make sure all super regs of reserved regs are marked reserved.

2018-01-24 18:09:53 +00:00

AMDGPURegisterInfo.h

[AMDGPU] Return true in enableMultipleCopyHints().

2018-02-17 10:00:28 +00:00

AMDGPURegisterInfo.td

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AMDGPURewriteOutArguments.cpp

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AMDGPUSubtarget.cpp

[AMDGPU][MC] Added validation of d16 and r128 modifiers of MIMG opcodes

2018-02-05 12:45:43 +00:00

AMDGPUSubtarget.h

[AMDGPU] Scratch setup fix on AMDPAL gfx9+ merge shader

2018-02-26 14:46:43 +00:00

AMDGPUTargetMachine.cpp

[AMDGPU] Change constant addr space to 4

2018-02-13 18:00:25 +00:00

AMDGPUTargetMachine.h

(Re-landing) Expose a TargetMachine::getTargetTransformInfo function

2017-12-22 18:21:59 +00:00

AMDGPUTargetObjectFile.cpp

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AMDGPUTargetObjectFile.h

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AMDGPUTargetTransformInfo.cpp

Revert "[AMDGPU] Increased vector length for global/constant loads."

2018-02-20 23:30:21 +00:00

AMDGPUTargetTransformInfo.h

Revert "[AMDGPU] Increased vector length for global/constant loads."

2018-02-20 23:30:21 +00:00

AMDGPUUnifyDivergentExitNodes.cpp

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AMDGPUUnifyMetadata.cpp

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AMDILCFGStructurizer.cpp

MachineFunction: Return reference from getFunction(); NFC

2017-12-15 22:22:58 +00:00

AMDKernelCodeT.h

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BUFInstructions.td

[AMDGPU][MC] Added lds support for MUBUF instructions

2018-02-21 13:13:48 +00:00

CaymanInstructions.td

[CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register.

2017-12-07 10:40:31 +00:00

CMakeLists.txt

AMDGPU: Partial ILP scheduler port from SelectionDAG to SchedulingDAG (experimental)

2017-11-20 14:35:53 +00:00

DSInstructions.td

AMDGPU: Stop using .NAME in .td files

2018-02-22 15:25:11 +00:00

EvergreenInstructions.td

AMDGPU: Select BFI patterns with 64-bit ints

2018-02-07 00:21:34 +00:00

FLATInstructions.td

[AMDGPU][MC][DISASSEMBLER][GFX9] Corrected decoding of GLOBAL/SCRATCH opcodes

2017-11-27 17:14:35 +00:00

GCNHazardRecognizer.cpp

[AMDGPU] Add GCNHazardRecognizer::checkInlineAsmHazards() and GCNHazardRecognizer::checkVALUHazardsHelper(). checkInlineAsmHazards() checks INLINEASM for hazards that we particularly care about (so not exhaustive); this patch adds a check for INLINEASM that defs vregs that hold data-to-be stored by immediately preceding store of more than 8 bytes. If the instr were not within an INLINEASM, this scenario would be handled by checkVALUHazard(). Add checkVALUHazardsHelper(), which will be called by both checkVALUHazards() and checkInlineAsmHazards().

2017-12-07 20:34:25 +00:00

GCNHazardRecognizer.h

[AMDGPU] Add GCNHazardRecognizer::checkInlineAsmHazards() and GCNHazardRecognizer::checkVALUHazardsHelper(). checkInlineAsmHazards() checks INLINEASM for hazards that we particularly care about (so not exhaustive); this patch adds a check for INLINEASM that defs vregs that hold data-to-be stored by immediately preceding store of more than 8 bytes. If the instr were not within an INLINEASM, this scenario would be handled by checkVALUHazard(). Add checkVALUHazardsHelper(), which will be called by both checkVALUHazards() and checkInlineAsmHazards().

2017-12-07 20:34:25 +00:00

GCNILPSched.cpp

AMDGPU: Partial ILP scheduler port from SelectionDAG to SchedulingDAG (experimental)

2017-11-20 14:35:53 +00:00

GCNIterativeScheduler.cpp

[NFC] fix trivial typos in comments and documents

2018-01-29 05:17:03 +00:00

GCNIterativeScheduler.h

AMDGPU: Partial ILP scheduler port from SelectionDAG to SchedulingDAG (experimental)

2017-11-20 14:35:53 +00:00

GCNMinRegStrategy.cpp

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GCNProcessors.td

AMDGPU: Bring processors and features in sync with the spec

2018-02-16 21:26:25 +00:00

GCNRegPressure.cpp

Rename LiveIntervalAnalysis.h to LiveIntervals.h

2017-12-13 02:51:04 +00:00

GCNRegPressure.h

Rename LiveIntervalAnalysis.h to LiveIntervals.h

2017-12-13 02:51:04 +00:00

GCNSchedStrategy.cpp

[NFC] fix trivial typos in comments

2018-01-22 05:54:46 +00:00

GCNSchedStrategy.h

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LLVMBuild.txt

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MIMGInstructions.td

[AMDGPU][MC] Added support of 64-bit image atomics

2018-01-26 15:43:29 +00:00

R600ClauseMergePass.cpp

MachineFunction: Return reference from getFunction(); NFC

2017-12-15 22:22:58 +00:00

R600ControlFlowFinalizer.cpp

MachineFunction: Return reference from getFunction(); NFC

2017-12-15 22:22:58 +00:00

R600Defines.h

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R600EmitClauseMarkers.cpp

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R600ExpandSpecialInstrs.cpp

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R600FrameLowering.cpp

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R600FrameLowering.h

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R600InstrFormats.td

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R600InstrInfo.cpp

[AMDGPU] Make sure all super regs of reserved regs are marked reserved.

2018-01-24 18:09:53 +00:00

R600InstrInfo.h

[AMDGPU] Make sure all super regs of reserved regs are marked reserved.

2018-01-24 18:09:53 +00:00

R600Instructions.td

AMDGPU: Move ADDRIndirect complex pattern into R600Instructions.td

2018-01-29 23:29:26 +00:00

R600Intrinsics.td

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R600ISelLowering.cpp

AMDGPU/EG: Add a new FeatureFMA and use it to selectively enable FMA instruction

2017-12-04 23:07:28 +00:00

R600ISelLowering.h

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R600MachineFunctionInfo.cpp

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R600MachineFunctionInfo.h

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R600MachineScheduler.cpp

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R600MachineScheduler.h

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R600OptimizeVectorRegisters.cpp

MachineFunction: Return reference from getFunction(); NFC

2017-12-15 22:22:58 +00:00

R600Packetizer.cpp

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R600Processors.td

AMDGPU/EG: Add a new FeatureFMA and use it to selectively enable FMA instruction

2017-12-04 23:07:28 +00:00

R600RegisterInfo.cpp

[AMDGPU] Make sure all super regs of reserved regs are marked reserved.

2018-01-24 18:09:53 +00:00

R600RegisterInfo.h

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R600RegisterInfo.td

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R600Schedule.td

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R700Instructions.td

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SIAnnotateControlFlow.cpp

AMDGPU: Error in SIAnnotateControlFlow instead of assert

2018-01-17 16:30:01 +00:00

SIDebuggerInsertNops.cpp

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SIDefines.h

AMDGPU/SI: Add d16 support for image intrinsics.

2018-01-18 22:08:53 +00:00

SIFixSGPRCopies.cpp

[CodeGen] Unify MBB reference format in both MIR and debug output

2017-12-04 17:18:51 +00:00

SIFixVGPRCopies.cpp

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SIFixWWMLiveness.cpp

Rename LiveIntervalAnalysis.h to LiveIntervals.h

2017-12-13 02:51:04 +00:00

SIFoldOperands.cpp

AMDGPU: Don't crash when trying to fold implicit operands

2018-02-08 01:12:46 +00:00

SIFrameLowering.cpp

[AMDGPU] Scratch setup fix on AMDPAL gfx9+ merge shader

2018-02-26 14:46:43 +00:00

SIFrameLowering.h

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SIInsertSkips.cpp

Fix compiler warning introduced in r325931. NFC.

2018-02-23 19:11:33 +00:00

SIInsertWaitcnts.cpp

[AMDGPU] Make note of existing waitcnt instrs; this is add-on work related to suppression of redundant waitcnt instrs. It is necessary to make note of these existing waitcnt instrs so that we do not fall into an infinite loop when handling loops. Also, [NFC] some minor code clean-up.

2018-02-19 19:19:59 +00:00

SIInsertWaits.cpp

[NFC] fix trivial typos in comments

2018-02-22 07:48:29 +00:00

SIInstrFormats.td

[MachineOperand][Target] MachineOperand::isRenamable semantics changes

2018-02-23 18:25:08 +00:00

SIInstrInfo.cpp

AMDGPU: Fix S_BUFFER_LOAD_DWORD_SGPR moveToVALU

2018-02-06 15:17:55 +00:00

SIInstrInfo.h

[AMDGPU][MC] Added lds support for MUBUF instructions

2018-02-21 13:13:48 +00:00

SIInstrInfo.td

[AMDGPU][MC] Added lds support for MUBUF instructions

2018-02-21 13:13:48 +00:00

SIInstructions.td

AMDGPU: Remove tied operand from si_else

2018-02-09 17:18:38 +00:00

SIIntrinsics.td

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SIISelLowering.cpp

AMDGPU/SI: Turn off GPR Indexing Mode immediately after the interested instruction.

2018-02-16 16:31:30 +00:00

SIISelLowering.h

AMDGPU/SI: Add d16 support for buffer intrinsics.

2018-01-12 21:12:19 +00:00

SILoadStoreOptimizer.cpp

AMDGPU: Track physreg uses in SILoadStoreOptimizer

2018-02-23 10:45:56 +00:00

SILowerControlFlow.cpp

Rename LiveIntervalAnalysis.h to LiveIntervals.h

2017-12-13 02:51:04 +00:00

SILowerI1Copies.cpp

Rename LiveIntervalAnalysis.h to LiveIntervals.h

2017-12-13 02:51:04 +00:00

SIMachineFunctionInfo.cpp

Reapply "AMDGPU: Add 32-bit constant address space"

2018-02-09 16:57:57 +00:00

SIMachineFunctionInfo.h

[AMDGPU] stop buffer_store being moved illegally

2018-02-20 10:03:38 +00:00

SIMachineScheduler.cpp

Rename LiveIntervalAnalysis.h to LiveIntervals.h

2017-12-13 02:51:04 +00:00

SIMachineScheduler.h

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SIMemoryLegalizer.cpp

[AMDGPU] More descriptive names in the memory legalizer

2018-02-09 06:05:33 +00:00

SIOptimizeExecMasking.cpp

[MachineOperand][Target] MachineOperand::isRenamable semantics changes

2018-02-23 18:25:08 +00:00

SIOptimizeExecMaskingPreRA.cpp

MachineFunction: Return reference from getFunction(); NFC

2017-12-15 22:22:58 +00:00

SIPeepholeSDWA.cpp

AMDGPU: Process SDWA block at a time

2018-02-08 22:46:41 +00:00

SIRegisterInfo.cpp

[AMDGPU] Make sure all super regs of reserved regs are marked reserved.

2018-01-24 18:09:53 +00:00

SIRegisterInfo.h

[AMDGPU] Make sure all super regs of reserved regs are marked reserved.

2018-01-24 18:09:53 +00:00

SIRegisterInfo.td

[AMDGPU][MC][GFX8][GFX9] Added XNACK_MASK support

2018-01-10 14:22:19 +00:00

SISchedule.td

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SIShrinkInstructions.cpp

[AMDGPU] Shrinking V_SUBBREV_U32

2018-02-24 01:32:32 +00:00

SIWholeQuadMode.cpp

MachineFunction: Return reference from getFunction(); NFC

2017-12-15 22:22:58 +00:00

SMInstructions.td

Reapply "AMDGPU: Add 32-bit constant address space"

2018-02-09 16:57:57 +00:00

SOPInstructions.td

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VIInstrFormats.td

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VIInstructions.td

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VOP1Instructions.td

[AMDGPU] Copy impdefs from pseudo to real instructions

2018-01-15 17:55:35 +00:00

VOP2Instructions.td

AMDGPU: Add intrinsics llvm.amdgcn.cvt.{pknorm.i16, pknorm.u16, pk.i16, pk.u16}

2018-01-31 20:18:04 +00:00

VOP3Instructions.td

[AMDGPU] isRenamable fixes to support copy forwarding

2018-01-30 17:37:39 +00:00

VOP3PInstructions.td

…

VOPCInstructions.td

[AMDGPU] Copy impdefs from pseudo to real instructions

2018-01-15 17:55:35 +00:00

VOPInstructions.td

[MachineOperand][Target] MachineOperand::isRenamable semantics changes

2018-02-23 18:25:08 +00:00