ac0f64f06d
Allocating wwm-registers and per-thread VGPR operands together imposes many challenges in the way the registers are reused during allocation. There are times when regalloc reuses the registers of regular VGPRs operations for wwm-operations in a small range leading to unwantedly clobbering their inactive lanes causing correctness issues that are hard to trace. This patch splits the VGPR allocation pipeline further to allocate wwm-registers first and the regular VGPR operands in a separate pipeline. The splitting would ensure that the physical registers used for wwm allocations won't take part in the next allocation pipeline to avoid any such clobbering.
496 lines
17 KiB
C++
496 lines
17 KiB
C++
//===-- AMDGPU.h - MachineFunction passes hw codegen --------------*- C++ -*-=//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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/// \file
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPU_H
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#define LLVM_LIB_TARGET_AMDGPU_AMDGPU_H
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#include "llvm/CodeGen/MachinePassManager.h"
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#include "llvm/IR/PassManager.h"
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#include "llvm/Pass.h"
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#include "llvm/Support/AMDGPUAddrSpace.h"
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#include "llvm/Support/CodeGen.h"
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namespace llvm {
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class AMDGPUTargetMachine;
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class GCNTargetMachine;
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class TargetMachine;
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// GlobalISel passes
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void initializeAMDGPUPreLegalizerCombinerPass(PassRegistry &);
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FunctionPass *createAMDGPUPreLegalizeCombiner(bool IsOptNone);
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void initializeAMDGPUPostLegalizerCombinerPass(PassRegistry &);
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FunctionPass *createAMDGPUPostLegalizeCombiner(bool IsOptNone);
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FunctionPass *createAMDGPURegBankCombiner(bool IsOptNone);
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void initializeAMDGPURegBankCombinerPass(PassRegistry &);
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void initializeAMDGPURegBankSelectPass(PassRegistry &);
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// SI Passes
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FunctionPass *createGCNDPPCombinePass();
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FunctionPass *createSIAnnotateControlFlowLegacyPass();
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FunctionPass *createSIFoldOperandsLegacyPass();
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FunctionPass *createSIPeepholeSDWALegacyPass();
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FunctionPass *createSILowerI1CopiesLegacyPass();
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FunctionPass *createAMDGPUGlobalISelDivergenceLoweringPass();
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FunctionPass *createSIShrinkInstructionsLegacyPass();
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FunctionPass *createSILoadStoreOptimizerLegacyPass();
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FunctionPass *createSIWholeQuadModePass();
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FunctionPass *createSIFixControlFlowLiveIntervalsPass();
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FunctionPass *createSIOptimizeExecMaskingPreRAPass();
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FunctionPass *createSIOptimizeVGPRLiveRangePass();
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FunctionPass *createSIFixSGPRCopiesLegacyPass();
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FunctionPass *createLowerWWMCopiesPass();
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FunctionPass *createSIMemoryLegalizerPass();
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FunctionPass *createSIInsertWaitcntsPass();
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FunctionPass *createSIPreAllocateWWMRegsPass();
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FunctionPass *createSIFormMemoryClausesPass();
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FunctionPass *createSIPostRABundlerPass();
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FunctionPass *createAMDGPUImageIntrinsicOptimizerPass(const TargetMachine *);
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ModulePass *createAMDGPURemoveIncompatibleFunctionsPass(const TargetMachine *);
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FunctionPass *createAMDGPUCodeGenPreparePass();
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FunctionPass *createAMDGPULateCodeGenPrepareLegacyPass();
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FunctionPass *createAMDGPUReserveWWMRegsPass();
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FunctionPass *createAMDGPURewriteOutArgumentsPass();
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ModulePass *
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createAMDGPULowerModuleLDSLegacyPass(const AMDGPUTargetMachine *TM = nullptr);
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ModulePass *createAMDGPULowerBufferFatPointersPass();
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FunctionPass *createSIModeRegisterPass();
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FunctionPass *createGCNPreRAOptimizationsPass();
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struct AMDGPUSimplifyLibCallsPass : PassInfoMixin<AMDGPUSimplifyLibCallsPass> {
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AMDGPUSimplifyLibCallsPass() {}
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PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
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};
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struct AMDGPUImageIntrinsicOptimizerPass
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: PassInfoMixin<AMDGPUImageIntrinsicOptimizerPass> {
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AMDGPUImageIntrinsicOptimizerPass(TargetMachine &TM) : TM(TM) {}
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PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
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private:
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TargetMachine &TM;
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};
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struct AMDGPUUseNativeCallsPass : PassInfoMixin<AMDGPUUseNativeCallsPass> {
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PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
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};
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class SILowerI1CopiesPass : public PassInfoMixin<SILowerI1CopiesPass> {
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public:
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SILowerI1CopiesPass() = default;
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PreservedAnalyses run(MachineFunction &MF,
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MachineFunctionAnalysisManager &MFAM);
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};
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void initializeAMDGPUDAGToDAGISelLegacyPass(PassRegistry &);
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void initializeAMDGPUAlwaysInlinePass(PassRegistry&);
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Pass *createAMDGPUAnnotateKernelFeaturesPass();
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Pass *createAMDGPUAttributorLegacyPass();
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void initializeAMDGPUAttributorLegacyPass(PassRegistry &);
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void initializeAMDGPUAnnotateKernelFeaturesPass(PassRegistry &);
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extern char &AMDGPUAnnotateKernelFeaturesID;
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// DPP/Iterative option enables the atomic optimizer with given strategy
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// whereas None disables the atomic optimizer.
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enum class ScanOptions { DPP, Iterative, None };
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FunctionPass *createAMDGPUAtomicOptimizerPass(ScanOptions ScanStrategy);
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void initializeAMDGPUAtomicOptimizerPass(PassRegistry &);
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extern char &AMDGPUAtomicOptimizerID;
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ModulePass *createAMDGPUCtorDtorLoweringLegacyPass();
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void initializeAMDGPUCtorDtorLoweringLegacyPass(PassRegistry &);
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extern char &AMDGPUCtorDtorLoweringLegacyPassID;
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FunctionPass *createAMDGPULowerKernelArgumentsPass();
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void initializeAMDGPULowerKernelArgumentsPass(PassRegistry &);
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extern char &AMDGPULowerKernelArgumentsID;
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FunctionPass *createAMDGPUPromoteKernelArgumentsPass();
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void initializeAMDGPUPromoteKernelArgumentsPass(PassRegistry &);
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extern char &AMDGPUPromoteKernelArgumentsID;
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struct AMDGPUPromoteKernelArgumentsPass
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: PassInfoMixin<AMDGPUPromoteKernelArgumentsPass> {
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PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
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};
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ModulePass *createAMDGPULowerKernelAttributesPass();
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void initializeAMDGPULowerKernelAttributesPass(PassRegistry &);
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extern char &AMDGPULowerKernelAttributesID;
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struct AMDGPULowerKernelAttributesPass
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: PassInfoMixin<AMDGPULowerKernelAttributesPass> {
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PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
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};
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void initializeAMDGPULowerModuleLDSLegacyPass(PassRegistry &);
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extern char &AMDGPULowerModuleLDSLegacyPassID;
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struct AMDGPULowerModuleLDSPass : PassInfoMixin<AMDGPULowerModuleLDSPass> {
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const AMDGPUTargetMachine &TM;
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AMDGPULowerModuleLDSPass(const AMDGPUTargetMachine &TM_) : TM(TM_) {}
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PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM);
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};
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void initializeAMDGPULowerBufferFatPointersPass(PassRegistry &);
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extern char &AMDGPULowerBufferFatPointersID;
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struct AMDGPULowerBufferFatPointersPass
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: PassInfoMixin<AMDGPULowerBufferFatPointersPass> {
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AMDGPULowerBufferFatPointersPass(const TargetMachine &TM) : TM(TM) {}
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PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM);
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private:
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const TargetMachine &TM;
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};
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void initializeAMDGPUReserveWWMRegsPass(PassRegistry &);
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extern char &AMDGPUReserveWWMRegsID;
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void initializeAMDGPURewriteOutArgumentsPass(PassRegistry &);
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extern char &AMDGPURewriteOutArgumentsID;
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void initializeGCNDPPCombineLegacyPass(PassRegistry &);
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extern char &GCNDPPCombineLegacyID;
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void initializeSIFoldOperandsLegacyPass(PassRegistry &);
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extern char &SIFoldOperandsLegacyID;
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void initializeSIPeepholeSDWALegacyPass(PassRegistry &);
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extern char &SIPeepholeSDWALegacyID;
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void initializeSIShrinkInstructionsLegacyPass(PassRegistry &);
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extern char &SIShrinkInstructionsLegacyID;
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void initializeSIFixSGPRCopiesLegacyPass(PassRegistry &);
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extern char &SIFixSGPRCopiesLegacyID;
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void initializeSIFixVGPRCopiesPass(PassRegistry &);
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extern char &SIFixVGPRCopiesID;
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void initializeSILowerWWMCopiesPass(PassRegistry &);
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extern char &SILowerWWMCopiesID;
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void initializeSILowerI1CopiesLegacyPass(PassRegistry &);
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extern char &SILowerI1CopiesLegacyID;
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void initializeAMDGPUGlobalISelDivergenceLoweringPass(PassRegistry &);
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extern char &AMDGPUGlobalISelDivergenceLoweringID;
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void initializeAMDGPUMarkLastScratchLoadPass(PassRegistry &);
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extern char &AMDGPUMarkLastScratchLoadID;
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void initializeSILowerSGPRSpillsLegacyPass(PassRegistry &);
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extern char &SILowerSGPRSpillsLegacyID;
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void initializeSILoadStoreOptimizerLegacyPass(PassRegistry &);
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extern char &SILoadStoreOptimizerLegacyID;
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void initializeSIWholeQuadModePass(PassRegistry &);
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extern char &SIWholeQuadModeID;
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void initializeSILowerControlFlowPass(PassRegistry &);
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extern char &SILowerControlFlowID;
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void initializeSIPreEmitPeepholePass(PassRegistry &);
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extern char &SIPreEmitPeepholeID;
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void initializeSILateBranchLoweringPass(PassRegistry &);
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extern char &SILateBranchLoweringPassID;
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void initializeSIOptimizeExecMaskingPass(PassRegistry &);
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extern char &SIOptimizeExecMaskingID;
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void initializeSIPreAllocateWWMRegsPass(PassRegistry &);
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extern char &SIPreAllocateWWMRegsID;
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void initializeAMDGPUImageIntrinsicOptimizerPass(PassRegistry &);
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extern char &AMDGPUImageIntrinsicOptimizerID;
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void initializeAMDGPUPerfHintAnalysisLegacyPass(PassRegistry &);
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extern char &AMDGPUPerfHintAnalysisLegacyID;
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void initializeGCNRegPressurePrinterPass(PassRegistry &);
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extern char &GCNRegPressurePrinterID;
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// Passes common to R600 and SI
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FunctionPass *createAMDGPUPromoteAlloca();
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void initializeAMDGPUPromoteAllocaPass(PassRegistry&);
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extern char &AMDGPUPromoteAllocaID;
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FunctionPass *createAMDGPUPromoteAllocaToVector();
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void initializeAMDGPUPromoteAllocaToVectorPass(PassRegistry&);
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extern char &AMDGPUPromoteAllocaToVectorID;
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struct AMDGPUPromoteAllocaPass : PassInfoMixin<AMDGPUPromoteAllocaPass> {
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AMDGPUPromoteAllocaPass(TargetMachine &TM) : TM(TM) {}
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PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
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private:
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TargetMachine &TM;
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};
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struct AMDGPUPromoteAllocaToVectorPass
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: PassInfoMixin<AMDGPUPromoteAllocaToVectorPass> {
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AMDGPUPromoteAllocaToVectorPass(TargetMachine &TM) : TM(TM) {}
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PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
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private:
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TargetMachine &TM;
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};
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struct AMDGPUAtomicOptimizerPass : PassInfoMixin<AMDGPUAtomicOptimizerPass> {
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AMDGPUAtomicOptimizerPass(TargetMachine &TM, ScanOptions ScanImpl)
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: TM(TM), ScanImpl(ScanImpl) {}
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PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
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private:
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TargetMachine &TM;
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ScanOptions ScanImpl;
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};
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Pass *createAMDGPUStructurizeCFGPass();
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FunctionPass *createAMDGPUISelDag(TargetMachine &TM, CodeGenOptLevel OptLevel);
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ModulePass *createAMDGPUAlwaysInlinePass(bool GlobalOpt = true);
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struct AMDGPUAlwaysInlinePass : PassInfoMixin<AMDGPUAlwaysInlinePass> {
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AMDGPUAlwaysInlinePass(bool GlobalOpt = true) : GlobalOpt(GlobalOpt) {}
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PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM);
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private:
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bool GlobalOpt;
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};
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void initializeAMDGPUSwLowerLDSLegacyPass(PassRegistry &);
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extern char &AMDGPUSwLowerLDSLegacyPassID;
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ModulePass *
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createAMDGPUSwLowerLDSLegacyPass(const AMDGPUTargetMachine *TM = nullptr);
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struct AMDGPUSwLowerLDSPass : PassInfoMixin<AMDGPUSwLowerLDSPass> {
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const AMDGPUTargetMachine &TM;
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AMDGPUSwLowerLDSPass(const AMDGPUTargetMachine &TM_) : TM(TM_) {}
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PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM);
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};
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class AMDGPUCodeGenPreparePass
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: public PassInfoMixin<AMDGPUCodeGenPreparePass> {
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private:
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TargetMachine &TM;
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public:
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AMDGPUCodeGenPreparePass(TargetMachine &TM) : TM(TM){};
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PreservedAnalyses run(Function &, FunctionAnalysisManager &);
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};
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class AMDGPULateCodeGenPreparePass
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: public PassInfoMixin<AMDGPULateCodeGenPreparePass> {
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private:
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const GCNTargetMachine &TM;
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public:
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AMDGPULateCodeGenPreparePass(const GCNTargetMachine &TM) : TM(TM) {};
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PreservedAnalyses run(Function &, FunctionAnalysisManager &);
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};
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class AMDGPULowerKernelArgumentsPass
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: public PassInfoMixin<AMDGPULowerKernelArgumentsPass> {
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private:
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TargetMachine &TM;
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public:
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AMDGPULowerKernelArgumentsPass(TargetMachine &TM) : TM(TM){};
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PreservedAnalyses run(Function &, FunctionAnalysisManager &);
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};
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struct AMDGPUAttributorOptions {
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bool IsClosedWorld = false;
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};
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class AMDGPUAttributorPass : public PassInfoMixin<AMDGPUAttributorPass> {
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private:
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TargetMachine &TM;
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AMDGPUAttributorOptions Options;
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public:
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AMDGPUAttributorPass(TargetMachine &TM, AMDGPUAttributorOptions Options = {})
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: TM(TM), Options(Options) {};
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PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM);
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};
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class AMDGPUAnnotateUniformValuesPass
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: public PassInfoMixin<AMDGPUAnnotateUniformValuesPass> {
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public:
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AMDGPUAnnotateUniformValuesPass() {}
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PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
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};
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FunctionPass *createAMDGPUAnnotateUniformValuesLegacy();
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ModulePass *createAMDGPUPrintfRuntimeBinding();
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void initializeAMDGPUPrintfRuntimeBindingPass(PassRegistry&);
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extern char &AMDGPUPrintfRuntimeBindingID;
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void initializeAMDGPUResourceUsageAnalysisPass(PassRegistry &);
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extern char &AMDGPUResourceUsageAnalysisID;
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struct AMDGPUPrintfRuntimeBindingPass
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: PassInfoMixin<AMDGPUPrintfRuntimeBindingPass> {
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PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM);
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};
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ModulePass* createAMDGPUUnifyMetadataPass();
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void initializeAMDGPUUnifyMetadataPass(PassRegistry&);
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extern char &AMDGPUUnifyMetadataID;
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struct AMDGPUUnifyMetadataPass : PassInfoMixin<AMDGPUUnifyMetadataPass> {
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PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM);
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};
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void initializeSIOptimizeExecMaskingPreRAPass(PassRegistry&);
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extern char &SIOptimizeExecMaskingPreRAID;
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void initializeSIOptimizeVGPRLiveRangePass(PassRegistry &);
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extern char &SIOptimizeVGPRLiveRangeID;
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void initializeAMDGPUAnnotateUniformValuesLegacyPass(PassRegistry &);
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extern char &AMDGPUAnnotateUniformValuesLegacyPassID;
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void initializeAMDGPUCodeGenPreparePass(PassRegistry&);
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extern char &AMDGPUCodeGenPrepareID;
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void initializeAMDGPURemoveIncompatibleFunctionsPass(PassRegistry &);
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extern char &AMDGPURemoveIncompatibleFunctionsID;
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void initializeAMDGPULateCodeGenPrepareLegacyPass(PassRegistry &);
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extern char &AMDGPULateCodeGenPrepareLegacyID;
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FunctionPass *createAMDGPURewriteUndefForPHILegacyPass();
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void initializeAMDGPURewriteUndefForPHILegacyPass(PassRegistry &);
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extern char &AMDGPURewriteUndefForPHILegacyPassID;
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class AMDGPURewriteUndefForPHIPass
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: public PassInfoMixin<AMDGPURewriteUndefForPHIPass> {
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public:
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AMDGPURewriteUndefForPHIPass() = default;
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PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
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};
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class SIAnnotateControlFlowPass
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: public PassInfoMixin<SIAnnotateControlFlowPass> {
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private:
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const AMDGPUTargetMachine &TM;
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public:
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SIAnnotateControlFlowPass(const AMDGPUTargetMachine &TM) : TM(TM) {}
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PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
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};
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void initializeSIAnnotateControlFlowLegacyPass(PassRegistry &);
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extern char &SIAnnotateControlFlowLegacyPassID;
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void initializeSIMemoryLegalizerPass(PassRegistry&);
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extern char &SIMemoryLegalizerID;
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void initializeSIModeRegisterPass(PassRegistry&);
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extern char &SIModeRegisterID;
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void initializeAMDGPUInsertDelayAluPass(PassRegistry &);
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extern char &AMDGPUInsertDelayAluID;
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void initializeSIInsertHardClausesPass(PassRegistry &);
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extern char &SIInsertHardClausesID;
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void initializeSIInsertWaitcntsPass(PassRegistry&);
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extern char &SIInsertWaitcntsID;
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void initializeSIFormMemoryClausesPass(PassRegistry&);
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extern char &SIFormMemoryClausesID;
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void initializeSIPostRABundlerPass(PassRegistry&);
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extern char &SIPostRABundlerID;
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void initializeGCNCreateVOPDPass(PassRegistry &);
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extern char &GCNCreateVOPDID;
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void initializeAMDGPUUnifyDivergentExitNodesPass(PassRegistry&);
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extern char &AMDGPUUnifyDivergentExitNodesID;
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ImmutablePass *createAMDGPUAAWrapperPass();
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void initializeAMDGPUAAWrapperPassPass(PassRegistry&);
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ImmutablePass *createAMDGPUExternalAAWrapperPass();
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void initializeAMDGPUExternalAAWrapperPass(PassRegistry&);
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void initializeAMDGPUArgumentUsageInfoPass(PassRegistry &);
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ModulePass *createAMDGPUOpenCLEnqueuedBlockLoweringPass();
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void initializeAMDGPUOpenCLEnqueuedBlockLoweringPass(PassRegistry &);
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extern char &AMDGPUOpenCLEnqueuedBlockLoweringID;
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void initializeGCNNSAReassignPass(PassRegistry &);
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extern char &GCNNSAReassignID;
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void initializeGCNPreRALongBranchRegPass(PassRegistry &);
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extern char &GCNPreRALongBranchRegID;
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void initializeGCNPreRAOptimizationsPass(PassRegistry &);
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extern char &GCNPreRAOptimizationsID;
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FunctionPass *createAMDGPUSetWavePriorityPass();
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void initializeAMDGPUSetWavePriorityPass(PassRegistry &);
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void initializeGCNRewritePartialRegUsesPass(llvm::PassRegistry &);
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extern char &GCNRewritePartialRegUsesID;
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namespace AMDGPU {
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enum TargetIndex {
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TI_CONSTDATA_START,
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TI_SCRATCH_RSRC_DWORD0,
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TI_SCRATCH_RSRC_DWORD1,
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TI_SCRATCH_RSRC_DWORD2,
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TI_SCRATCH_RSRC_DWORD3
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};
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static inline bool addrspacesMayAlias(unsigned AS1, unsigned AS2) {
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static_assert(AMDGPUAS::MAX_AMDGPU_ADDRESS <= 9, "Addr space out of range");
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if (AS1 > AMDGPUAS::MAX_AMDGPU_ADDRESS || AS2 > AMDGPUAS::MAX_AMDGPU_ADDRESS)
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return true;
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// This array is indexed by address space value enum elements 0 ... to 9
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// clang-format off
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static const bool ASAliasRules[10][10] = {
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/* Flat Global Region Group Constant Private Const32 BufFatPtr BufRsrc BufStrdPtr */
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/* Flat */ {true, true, false, true, true, true, true, true, true, true},
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/* Global */ {true, true, false, false, true, false, true, true, true, true},
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/* Region */ {false, false, true, false, false, false, false, false, false, false},
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/* Group */ {true, false, false, true, false, false, false, false, false, false},
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/* Constant */ {true, true, false, false, false, false, true, true, true, true},
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/* Private */ {true, false, false, false, false, true, false, false, false, false},
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/* Constant 32-bit */ {true, true, false, false, true, false, false, true, true, true},
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/* Buffer Fat Ptr */ {true, true, false, false, true, false, true, true, true, true},
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/* Buffer Resource */ {true, true, false, false, true, false, true, true, true, true},
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/* Buffer Strided Ptr */ {true, true, false, false, true, false, true, true, true, true},
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};
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// clang-format on
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return ASAliasRules[AS1][AS2];
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}
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}
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} // End namespace llvm
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#endif
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