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llvm-project/llvm/test/CodeGen
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Arthur Eubanks c2ef06d3dd [NewPM] Port infer-address-spaces 
And add it to the AMDGPU opt pipeline.

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D93880
2020-12-28 19:58:12 -08:00
..
AArch64
[AArch64] Fix legalization of i128 ctpop without neon
2020-12-27 17:24:41 +01:00
AMDGPU
[NewPM] Port infer-address-spaces
2020-12-28 19:58:12 -08:00
ARC
…
ARM
[ARM] Add some NEON anyextend testing. NFC
2020-12-27 13:18:10 +00:00
AVR
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BPF
[BPF] support atomic instructions
2020-12-03 07:38:00 -08:00
Generic
Moved dwarf_eh_resume.ll from Generic to X86 folder
2020-12-24 20:08:50 +07:00
Hexagon
[Hexagon] Rename test case, NFC
2020-12-15 19:05:31 -06:00
Inputs
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Lanai
…
Mips
Revert "[FastISel] Flush local value map on ever instruction" and dependent patches
2020-12-01 14:26:23 -08:00
MIR
[MIRPrinter] Fix incorrect output of unnamed stack names
2020-12-28 18:01:40 +01:00
MSP430
OpaquePtr: Bulk update tests to use typed sret
2020-11-20 17:58:26 -05:00
NVPTX
OpaquePtr: Bulk update tests to use typed byval
2020-11-20 14:00:46 -05:00
PowerPC
[PowerPC] Do not emit HW loop when TLS var accessed in PHI of loop exit
2020-12-28 20:36:16 -06:00
RISCV
[RISCV] Define vmclr.m/vmset.m intrinsics.
2020-12-28 18:57:17 -08:00
SPARC
[BPI] Improve static heuristics for "cold" paths.
2020-12-23 22:47:36 +07:00
SystemZ
[DAGCombiner] Don't create sexts of deleted xors when they were in-visit replaced
2020-12-23 16:16:26 -08:00
Thumb
OpaquePtr: Update more tests to use typed sret
2020-11-20 20:08:43 -05:00
Thumb2
[ARM] Add bank conflict hazarding
2020-12-23 14:00:59 +00:00
VE
[VE] Vector 'and' isel and tests
2020-12-23 13:29:29 +01:00
WebAssembly
[WebAssembly] Prototype extending pairwise add instructions
2020-12-28 14:11:14 -08:00
WinCFGuard
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WinEH
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X86
Moved dwarf_eh_resume.ll from Generic to X86 folder
2020-12-24 20:08:50 +07:00
XCore
MCContext::reportError: don't call report_fatal_error
2020-12-20 23:23:12 -08:00