Stanislav Mekhanoshin c328c5d911

[AMDGPU] Combine to bf16 reciprocal square root. (#154185) ...

Co-authored-by: Ivan Kosarev <Ivan.Kosarev@amd.com>

Co-authored-by: Ivan Kosarev <Ivan.Kosarev@amd.com>

2025-08-18 13:07:20 -07:00

..

AArch64

[DAG] Fold trunc(avg(x,y)) for avgceil/floor u/s nodes if they have sufficient leading zero/sign bits (#152273)

2025-08-18 16:36:26 +01:00

AMDGPU

[AMDGPU] Combine to bf16 reciprocal square root. (#154185)

2025-08-18 13:07:20 -07:00

ARC

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ARM

[SimplifyCFG] Avoid threading for loop headers (#151142)

2025-08-18 09:46:55 +00:00

AVR

[Test] Add and update tests for lrint/llrint (NFC) (#152662)

2025-08-12 09:56:51 +09:00

BPF

[IR] Remove size argument from lifetime intrinsics (#150248)

2025-08-08 11:09:34 +02:00

CSKY

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DirectX

[DirectX] Add GlobalDCE pass after finalize linkage pass in DirectX backend (#151071)

2025-08-15 10:45:34 -07:00

Generic

[SPARC] Change half to use soft promotion rather than PromoteFloat (#152727)

2025-08-18 20:56:24 +02:00

Hexagon

[MIR] Remove std::variant from multiple save/restore point handling [nfc] (#153226)

2025-08-12 11:23:05 -07:00

Inputs

CodeGen: Convert test to opaque pointers (#147886)

2025-07-10 17:01:19 +09:00

Lanai

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LoongArch

[LoongArch] Always emit symbol-based relocations regardless of relaxation (#153943)

2025-08-18 20:15:49 +08:00

M68k

[M68k] Add anyext patterns for PCD addressing mode (#150356)

2025-08-16 23:33:47 +00:00

Mips

[CodeGen][Mips] Remove fp128 libcall list (#153798)

2025-08-18 09:22:41 +02:00

MIR

[MIR] Remove std::variant from multiple save/restore point handling [nfc] (#153226)

2025-08-12 11:23:05 -07:00

MLRegAlloc

[mlgo] Fix test post - #147716 (#148259)

2025-07-12 12:24:01 +02:00

MSP430

[Test] Add and update tests for lrint/llrint (NFC) (#152662)

2025-08-12 09:56:51 +09:00

NVPTX

[NVPTX] Do not mark move of global address as cheap enabling more CSE (#153730)

2025-08-15 10:17:34 -07:00

PowerPC

[llvm][LICM] Limit multi-use BOAssociation to FP and Vector (#149829)

2025-08-14 11:56:55 +01:00

RISCV

[RISCV][GISel] Optimize +0.0 to use fcvt.d.w for s64 on rv32 (#153978)

2025-08-18 17:52:24 +00:00

SPARC

[SPARC] Change half to use soft promotion rather than PromoteFloat (#152727)

2025-08-18 20:56:24 +02:00

SPIRV

[SPIRV] Filter disallowed extensions for env (#150051)

2025-08-18 18:33:58 +00:00

SystemZ

[SystemZ] Allow forming overflow op for i128 (#153557)

2025-08-14 16:15:22 +02:00

Thumb

[ARM] Have custom lowering for ucmp and scmp (#149315)

2025-08-08 06:51:18 +01:00

Thumb2

[AMDGPU] Avoid put implicit_def into bundle that break reg's liveness (#142563)

2025-08-13 10:41:44 +08:00

VE

[MIR] Remove std::variant from multiple save/restore point handling [nfc] (#153226)

2025-08-12 11:23:05 -07:00

WebAssembly

[WebAssembly] Reapply #149461 with correct CondCode in combine of SETCC (#153703)

2025-08-15 12:06:47 -07:00

WinCFGuard

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WinEH

Fix Windows EH IP2State tables (remove +1 bias) (#144745)

2025-07-22 09:18:13 -07:00

X86

[X86] Remove TuningPOPCNTFalseDeps from AlderLake (#154004)

2025-08-18 06:31:16 -07:00

XCore

XCore: Fix broken check lines in test

2025-08-04 08:40:48 +09:00

Xtensa

[Xtensa] Add esp32/esp8266 cpus implementation. (#152409)

2025-08-12 15:17:36 +03:00