Sudharsan Veeravalli c4645ffeda

[RISCV] Add Qualcomm uC Xqcicsr (CSR) extension (#117169) ...

The Qualcomm uC Xqcicsr extension adds 2 instructions that can read and
write CSRs.

The current spec can be found at:
https://github.com/quic/riscv-unified-db/releases/latest

This patch adds assembler only support.

2024-11-28 12:46:15 +05:30

..

AsmParser

[RISCV] Merge GPRPair and GPRF64Pair (#116094)

2024-11-20 10:08:55 +00:00

Disassembler

[RISCV] Add Qualcomm uC Xqcicsr (CSR) extension (#117169)

2024-11-28 12:46:15 +05:30

GISel

[RISCV][GISel] Support libcalls for f32/f64 acos/asin/atan/atan2/cosh/sinh/tanh.

2024-11-27 12:23:12 -08:00

MCA

…

MCTargetDesc

Reapply "[RISCV] Implement tail call optimization in machine outliner" (#117700)

2024-11-26 23:39:45 +08:00

TargetInfo

…

CMakeLists.txt

[RISCV] Introduce VLOptimizer pass (#108640)

2024-10-11 09:45:35 -04:00

RISCV.h

[RISCV] Introduce VLOptimizer pass (#108640)

2024-10-11 09:45:35 -04:00

RISCV.td

…

RISCVAsmPrinter.cpp

[RISCV] Remove unused includes (NFC) (#115814)

2024-11-11 22:54:54 -08:00

RISCVCallingConv.cpp

…

RISCVCallingConv.h

…

RISCVCallingConv.td

…

RISCVCodeGenPrepare.cpp

[RISCV] Remove unused includes (NFC) (#115814)

2024-11-11 22:54:54 -08:00

RISCVCombine.td

[RISCV] Remove constant_fold_cast_op from RISCVPostLegalizerCombiner.

2024-11-12 23:28:48 -08:00

RISCVConstantPoolValue.cpp

[RISCV] Remove unused includes (NFC) (#115814)

2024-11-11 22:54:54 -08:00

RISCVConstantPoolValue.h

…

RISCVDeadRegisterDefinitions.cpp

[RISCV] Remove unused includes (NFC) (#115814)

2024-11-11 22:54:54 -08:00

RISCVExpandAtomicPseudoInsts.cpp

…

RISCVExpandPseudoInsts.cpp

[RISCV] Teach expandRV32ZdinxStore to handle memoperand not being present. (#113981)

2024-10-28 22:37:47 -07:00

RISCVFeatures.td

[RISCV] Add Qualcomm uC Xqcicsr (CSR) extension (#117169)

2024-11-28 12:46:15 +05:30

RISCVFrameLowering.cpp

[RISCV] Use RISCVSubtarget::is64Bit() instead of hasFeature(RISCV::Feature64Bit). NFC

2024-11-27 14:02:15 -08:00

RISCVFrameLowering.h

[RISCV] Consolidate VLS codepaths in stack frame manipulation [nfc] (#117605)

2024-11-25 12:40:37 -08:00

RISCVGatherScatterLowering.cpp

[RISCV] Remove unused includes (NFC) (#115814)

2024-11-11 22:54:54 -08:00

RISCVGISel.td

[RISCV][GISel] Add atomic load/store test. Add additional atomic load/store isel patterns."

2024-11-20 22:23:18 -08:00

RISCVIndirectBranchTracking.cpp

[RISCV] Remove unused includes (NFC) (#115814)

2024-11-11 22:54:54 -08:00

RISCVInsertReadWriteCSR.cpp

…

RISCVInsertVSETVLI.cpp

[RISCV][NFC] Remove the unused RISCV_COALESCE_VSETVLI_NAME (#111536)

2024-10-08 19:53:34 +02:00

RISCVInsertWriteVXRM.cpp

[RISCV] Allow hoisting VXRM writes out of loops speculatively (#110044)

2024-11-27 13:31:39 -08:00

RISCVInstrFormats.td

[RISCV][MC] Support Assembling 48- and 64-bit Instructions (#110022)

2024-10-08 14:09:07 +01:00

RISCVInstrFormatsC.td

…

RISCVInstrFormatsV.td

…

RISCVInstrGISel.td

[RISCV][GISel] Custom promote s32 G_SHL/ASHR/LSHR on RV64. (#115559)

2024-11-11 20:59:21 -08:00

RISCVInstrInfo.cpp

Reapply "[RISCV] Implement tail call optimization in machine outliner" (#117700)

2024-11-26 23:39:45 +08:00

RISCVInstrInfo.h

[TTI][RISCV] Unconditionally break critical edges to sink ADDI (#108889)

2024-11-25 18:59:31 -08:00

RISCVInstrInfo.td

[RISCV] Add Qualcomm uC Xqcicsr (CSR) extension (#117169)

2024-11-28 12:46:15 +05:30

RISCVInstrInfoA.td

[RISCV] Make A implies Zaamo and Zalrsc (#116907)

2024-11-22 10:35:38 +08:00

RISCVInstrInfoC.td

[RISCV] Only allow 5 bit shift amounts in disassembler for RV32. (#115432)

2024-11-08 09:12:25 -08:00

RISCVInstrInfoD.td

[RISCV][GISel] Add register class to some isel output patterns so they can be imported.

2024-11-24 19:29:52 -08:00

RISCVInstrInfoF.td

[RISCV][GISel] Add register class to some isel output patterns so they can be imported.

2024-11-24 19:29:52 -08:00

RISCVInstrInfoM.td

…

RISCVInstrInfoSFB.td

[RISCV] Add OperandType for condition code arguments used by select and SFB pseudos. (#114163)

2024-10-29 21:23:31 -07:00

RISCVInstrInfoV.td

[RISCV] Avoid redundant SchedRead on _TIED VPseudos (#113940)

2024-10-29 10:49:35 -07:00

RISCVInstrInfoVPseudos.td

[RISCV] Use getSignedTargetConstant. NFC

2024-11-18 12:20:44 -08:00

RISCVInstrInfoVSDPatterns.td

[RISCV] Fix some isel patterns that used a type where we normally put a regclass. NFC

2024-11-08 18:11:39 -08:00

RISCVInstrInfoVVLPatterns.td

[RISCV] Use integer VTypeInfo predicate for vmv_v_v_vl pattern (#114915)

2024-11-05 13:01:36 +08:00

RISCVInstrInfoXCV.td

[RISCV] Add OperandType for condition code arguments used by select and SFB pseudos. (#114163)

2024-10-29 21:23:31 -07:00

RISCVInstrInfoXqci.td

[RISCV] Add Qualcomm uC Xqcicsr (CSR) extension (#117169)

2024-11-28 12:46:15 +05:30

RISCVInstrInfoXSf.td

[RISCV] Add hasPostISelHook to sf.vfnrclip pseudo instructions. (#114274)

2024-10-30 11:52:49 -07:00

RISCVInstrInfoXTHead.td

[RISCV] Add IsRV32 some patterns in RISCVInstrInfoXTHead.td.

2024-11-19 21:41:14 -08:00

RISCVInstrInfoXVentana.td

…

RISCVInstrInfoXwch.td

…

RISCVInstrInfoZa.td

…

RISCVInstrInfoZalasr.td

…

RISCVInstrInfoZb.td

[RISCV] Use the OperandTransform field of a couple PatLeafs to simplify isel patterns. NFC

2024-11-18 16:37:48 -08:00

RISCVInstrInfoZc.td

…

RISCVInstrInfoZcmop.td

…

RISCVInstrInfoZfa.td

[RISCV] Add OperandType to loadfpimm. (#114150)

2024-10-29 19:42:35 -07:00

RISCVInstrInfoZfbfmin.td

…

RISCVInstrInfoZfh.td

[RISCV][GISel] Add register class to some isel output patterns so they can be imported.

2024-11-24 19:29:52 -08:00

RISCVInstrInfoZicbo.td

…

RISCVInstrInfoZicfiss.td

…

RISCVInstrInfoZicond.td

…

RISCVInstrInfoZimop.td

…

RISCVInstrInfoZk.td

[RISCV] Combine RVBUnary and RVKUnary into classes that are more similar to ALU(W)_r(r/i). NFC (#111279)

2024-10-06 11:47:30 -07:00

RISCVInstrInfoZvfbf.td

…

RISCVInstrInfoZvk.td

[RISCV] Assign separate PseudoVSHA2MS_VV opcodes for each SEW (#114317)

2024-10-31 10:21:14 -07:00

RISCVISelDAGToDAG.cpp

[RISCV] Merge GPRPair and GPRF64Pair (#116094)

2024-11-20 10:08:55 +00:00

RISCVISelDAGToDAG.h

…

RISCVISelLowering.cpp

Fix a build warning introduce by my febbf910

2024-11-27 13:41:29 -08:00

RISCVISelLowering.h

[RISCV] Add an implementation of findRepresentativeClass to assign i32 to GPRRegClass for RV64. (#116165)

2024-11-18 10:07:20 -08:00

RISCVLandingPadSetup.cpp

[RISCV] Remove unused includes (NFC) (#115814)

2024-11-11 22:54:54 -08:00

RISCVMachineFunctionInfo.cpp

…

RISCVMachineFunctionInfo.h

…

RISCVMacroFusion.td

…

RISCVMakeCompressible.cpp

…

RISCVMergeBaseOffset.cpp

…

RISCVMoveMerger.cpp

…

RISCVOptWInstrs.cpp

…

RISCVPostRAExpandPseudoInsts.cpp

[RISCV] Remove unused includes (NFC) (#115814)

2024-11-11 22:54:54 -08:00

RISCVProcessors.td

[RISCV] Rename some Feature* to Tune* (#117966)

2024-11-28 15:01:49 +08:00

RISCVProfiles.td

[RISCV] Use the 'B' extension in RISC-V profile definitions (#113942)

2024-11-10 07:18:05 +00:00

RISCVPushPopOptimizer.cpp

…

RISCVRedundantCopyElimination.cpp

…

RISCVRegisterInfo.cpp

[RISCV] Fix a warning

2024-11-25 12:57:05 -08:00

RISCVRegisterInfo.h

[RISCV] Correct the precedence in isVRegClass (#116579)

2024-11-18 18:12:57 +08:00

RISCVRegisterInfo.td

[RISCV] Merge GPRPair and GPRF64Pair (#116094)

2024-11-20 10:08:55 +00:00

RISCVSchedRocket.td

…

RISCVSchedSiFive7.td

[llvm][NFC] Fix typos: replace “avaliable” with “available” across various files (#114524)

2024-11-01 13:25:04 +00:00

RISCVSchedSiFiveP400.td

[RISCV] Fix the worst case for VSHA2MS in SiFive P400/P600 scheduling models (#116893)

2024-11-21 10:59:46 -08:00

RISCVSchedSiFiveP600.td

[RISCV] Fix the worst case for VSHA2MS in SiFive P400/P600 scheduling models (#116893)

2024-11-21 10:59:46 -08:00

RISCVSchedSyntacoreSCR1.td

…

RISCVSchedSyntacoreSCR7.td

…

RISCVSchedSyntacoreSCR345.td

…

RISCVSchedule.td

…

RISCVScheduleV.td

[RISCV] Assign different scheduling classes for VMADC/VMSBC (#113009)

2024-10-28 09:37:54 -07:00

RISCVScheduleXSf.td

…

RISCVScheduleZb.td

…

RISCVScheduleZvk.td

[RISCV] Assign separate PseudoVSHA2MS_VV opcodes for each SEW (#114317)

2024-10-31 10:21:14 -07:00

RISCVSchedXiangShanNanHu.td

…

RISCVSubtarget.cpp

[RISCV] Remove getPostRAMutations (#117527)

2024-11-26 10:55:43 +08:00

RISCVSubtarget.h

[RISCV] Remove getPostRAMutations (#117527)

2024-11-26 10:55:43 +08:00

RISCVSystemOperands.td

…

RISCVTargetMachine.cpp

[RISCV] Enable global merging by default (#115495)

2024-11-15 13:22:34 +00:00

RISCVTargetMachine.h

Overhaul the TargetMachine and LLVMTargetMachine Classes (#111234)

2024-11-14 13:30:05 -08:00

RISCVTargetObjectFile.cpp

…

RISCVTargetObjectFile.h

…

RISCVTargetTransformInfo.cpp

[RISCV][CostModel] add cost for cttz/ctlz under the non-zvbb (#117515)

2024-11-26 11:40:52 +08:00

RISCVTargetTransformInfo.h

[llvm] Add BasicTTIImpl::areInlineCompatible for target feature subset checks (#117493)

2024-11-25 11:22:49 +08:00

RISCVVectorPeephole.cpp

[RISCV] Remove unused includes (NFC) (#115814)

2024-11-11 22:54:54 -08:00

RISCVVLOptimizer.cpp

[RISCV] Remove unused includes (NFC) (#115814)

2024-11-11 22:54:54 -08:00

RISCVZacasABIFix.cpp

[RISCV] Remove unused includes (NFC) (#115814)

2024-11-11 22:54:54 -08:00