c482b8faea
Instead of executing the whole entry VPIRBB twice, first only execute the VPExpandSCEVRecipes and replace their uses with the expanded VPValue, which will be a live-in. This allows removing special logic in VPExpandSCEVRecipe to support executing twice and allows moving the ExpandedSCEVs map out of VPTransformState. It will also allow adding other recipes to the entry VPBB in the future.
137 lines
4.8 KiB
LLVM
137 lines
4.8 KiB
LLVM
; REQUIRES: asserts
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; RUN: opt -p loop-vectorize -force-vector-width=2 -force-vector-interleave=1 -debug -disable-output %s 2>&1 | FileCheck %s
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define void @switch4_default_common_dest_with_case(ptr %start, ptr %end) {
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; CHECK: VPlan 'Final VPlan for VF={2},UF={1}' {
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; CHECK-NEXT: Live-in ir<[[VFxUF:.+]]> = VF * UF
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; CHECK-NEXT: Live-in ir<[[VTC:%.+]]> = vector-trip-count
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; CHECK-NEXT: ir<%0> = original trip-count
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; CHECK-EMPTY:
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; CHECK-NEXT: ir-bb<entry>:
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; CHECK-NEXT: Successor(s): ir-bb<scalar.ph>, ir-bb<vector.ph>
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; CHECK-EMPTY:
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; CHECK-NEXT: ir-bb<vector.ph>:
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; CHECK-NEXT: IR %n.mod.vf = urem i64 %0, 2
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; CHECK-NEXT: IR %n.vec = sub i64 %0, %n.mod.vf
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; CHECK-NEXT: vp<[[END:%.+]]> = DERIVED-IV ir<%start> + ir<%n.vec> * ir<1>
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; CHECK-NEXT: Successor(s): vector loop
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; CHECK-EMPTY:
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; CHECK-NEXT: <x1> vector loop: {
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; CHECK-NEXT: vector.body:
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; CHECK-NEXT: EMIT vp<[[CAN_IV:%.+]]> = phi ir<0>, vp<[[CAN_IV_NEXT:%.+]]>
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; CHECK-NEXT: vp<[[STEPS:%.+]]> = SCALAR-STEPS vp<[[CAN_IV]]>, ir<1>
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; CHECK-NEXT: EMIT vp<[[PTR:%.+]]> = ptradd ir<%start>, vp<[[STEPS]]>
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; CHECK-NEXT: vp<[[WIDE_PTR:%.+]]> = vector-pointer vp<[[PTR]]>
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; CHECK-NEXT: WIDEN ir<%l> = load vp<[[WIDE_PTR]]>
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; CHECK-NEXT: EMIT vp<[[C1:%.+]]> = icmp eq ir<%l>, ir<-12>
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; CHECK-NEXT: EMIT vp<[[C2:%.+]]> = icmp eq ir<%l>, ir<13>
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; CHECK-NEXT: EMIT vp<[[OR_CASES:%.+]]> = or vp<[[C1]]>, vp<[[C2]]>
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; CHECK-NEXT: EMIT vp<[[DEFAULT_MASK:%.+]]> = not vp<[[OR_CASES]]>
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; CHECK-NEXT: Successor(s): pred.store
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; CHECK-EMPTY:
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; CHECK-NEXT: <xVFxUF> pred.store: {
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; CHECK-NEXT: pred.store.entry:
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; CHECK-NEXT: BRANCH-ON-MASK vp<[[C2]]>
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; CHECK-NEXT: Successor(s): pred.store.if, pred.store.continue
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; CHECK-EMPTY:
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; CHECK-NEXT: pred.store.if:
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; CHECK-NEXT: REPLICATE store ir<0>, vp<[[PTR]]>
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; CHECK-NEXT: Successor(s): pred.store.continue
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; CHECK-EMPTY:
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; CHECK-NEXT: pred.store.continue:
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; CHECK-NEXT: No successors
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; CHECK-NEXT: }
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; CHECK-NEXT: Successor(s): if.then.2.0
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; CHECK-EMPTY:
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; CHECK-NEXT: if.then.2.0:
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; CHECK-NEXT: Successor(s): pred.store
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; CHECK-EMPTY:
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; CHECK-NEXT: <xVFxUF> pred.store: {
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; CHECK-NEXT: pred.store.entry:
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; CHECK-NEXT: BRANCH-ON-MASK vp<[[C1]]>
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; CHECK-NEXT: Successor(s): pred.store.if, pred.store.continue
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; CHECK-EMPTY:
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; CHECK-NEXT: pred.store.if:
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; CHECK-NEXT: REPLICATE store ir<42>, vp<[[PTR]]>
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; CHECK-NEXT: Successor(s): pred.store.continue
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; CHECK-EMPTY:
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; CHECK-NEXT: pred.store.continue:
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; CHECK-NEXT: No successors
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; CHECK-NEXT: }
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; CHECK-NEXT: Successor(s): if.then.1.1
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; CHECK-EMPTY:
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; CHECK-NEXT: if.then.1.1:
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; CHECK-NEXT: Successor(s): pred.store
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; CHECK-EMPTY:
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; CHECK-NEXT: <xVFxUF> pred.store: {
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; CHECK-NEXT: pred.store.entry:
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; CHECK-NEXT: BRANCH-ON-MASK vp<[[DEFAULT_MASK]]>
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; CHECK-NEXT: Successor(s): pred.store.if, pred.store.continue
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; CHECK-EMPTY:
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; CHECK-NEXT: pred.store.if:
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; CHECK-NEXT: REPLICATE store ir<2>, vp<[[PTR]]>
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; CHECK-NEXT: Successor(s): pred.store.continue
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; CHECK-EMPTY:
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; CHECK-NEXT: pred.store.continue:
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; CHECK-NEXT: No successors
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; CHECK-NEXT: }
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; CHECK-NEXT: Successor(s): default.2
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; CHECK-EMPTY:
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; CHECK-NEXT: default.2:
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; CHECK-NEXT: EMIT vp<[[CAN_IV_NEXT]]> = add nuw vp<[[CAN_IV]]>, ir<[[VFxUF]]>
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; CHECK-NEXT: EMIT branch-on-count vp<[[CAN_IV_NEXT]]>, ir<[[VTC]]>
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; CHECK-NEXT: No successors
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; CHECK-NEXT: }
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; CHECK-NEXT: Successor(s): middle.block
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; CHECK-EMPTY:
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; CHECK-NEXT: middle.block:
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; CHECK-NEXT: EMIT vp<[[MIDDLE_CMP:%.+]]> = icmp eq ir<%0>, ir<[[VTC]]>
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; CHECK-NEXT: EMIT branch-on-cond vp<[[MIDDLE_CMP]]>
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; CHECK-NEXT: Successor(s): ir-bb<exit>, ir-bb<scalar.ph>
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; CHECK-EMPTY:
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; CHECK-NEXT: ir-bb<exit>:
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; CHECK-NEXT: No successors
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; CHECK-EMPTY:
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; CHECK-NEXT: ir-bb<scalar.ph>:
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; CHECK-NEXT: EMIT vp<[[RESUME:%.+]]> = resume-phi vp<[[END]]>, ir<%start>
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; CHECK-NEXT: Successor(s): ir-bb<loop.header>
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; CHECK-EMPTY:
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; CHECK-NEXT: ir-bb<loop.header>:
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; CHECK-NEXT: IR %ptr.iv = phi ptr [ %start, %scalar.ph ], [ %ptr.iv.next, %loop.latch ] (extra operand: vp<[[RESUME]]> from ir-bb<scalar.ph>)
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; CHECK-NEXT: IR %l = load i8, ptr %ptr.iv, align 1
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; CHECK-NEXT: No successors
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; CHECK-NEXT: }
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;
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entry:
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br label %loop.header
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loop.header:
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%ptr.iv = phi ptr [ %start, %entry ], [ %ptr.iv.next, %loop.latch ]
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%l = load i8, ptr %ptr.iv, align 1
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switch i8 %l, label %default [
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i8 -12, label %if.then.1
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i8 13, label %if.then.2
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i8 0, label %default
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]
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if.then.1:
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store i8 42, ptr %ptr.iv, align 1
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br label %loop.latch
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if.then.2:
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store i8 0, ptr %ptr.iv, align 1
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br label %loop.latch
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default:
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store i8 2, ptr %ptr.iv, align 1
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br label %loop.latch
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loop.latch:
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%ptr.iv.next = getelementptr inbounds i8, ptr %ptr.iv, i64 1
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%ec = icmp eq ptr %ptr.iv.next, %end
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br i1 %ec, label %exit, label %loop.header
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exit:
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ret void
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}
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