c4b002bf5a
In some cases, the code generator attempts to generate instructions such as: lddw r24, Y+63 which expands to: ldd r24, Y+63 ldd r25, Y+64 # Oops! This is actually ld r25, Y in the binary This commit limits the first offset to 62, and thus the second to 63. It also updates some asserts in AVRExpandPseudoInsts.cpp, including for INW and OUTW, which appear to be unused. Patch by Thomas Backman. llvm-svn: 314890
19 lines
576 B
LLVM
19 lines
576 B
LLVM
; RUN: llc -O0 < %s -march=avr | FileCheck %s
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define i32 @std_ldd_overflow() {
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%src = alloca [4 x i8]
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%dst = alloca [4 x i8]
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%buf = alloca [28 x i16]
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%1 = bitcast [4 x i8]* %src to i32*
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store i32 0, i32 *%1
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%2 = bitcast [4 x i8]* %dst to i8*
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%3 = bitcast [4 x i8]* %src to i8*
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call void @llvm.memcpy.p0i8.p0i8.i16(i8* %2, i8* %3, i16 4, i32 1, i1 false)
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; CHECK-NOT: std {{[XYZ]}}+64, {{r[0-9]+}}
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; CHECK-NOT: ldd {{r[0-9]+}}, {{[XYZ]}}+64
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ret i32 0
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}
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declare void @llvm.memcpy.p0i8.p0i8.i16(i8* nocapture writeonly, i8* nocapture readonly, i16, i32, i1)
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