Simon Pilgrim c4eec9eb52

[X86] combineConcatVectorOps - add concatenation handling for consecutive extracts of upper subvectors (#132389) ...

We already fold concat(extract_subvector(x,0), extract_subvector(x,numsubelts)) -> (wider lower half) extract_subvector(x,0)

This patch extends this handling for the concat(extract_subvector(x,c), extract_subvector(x,c+numsubelts)) -> (wider upper half) extract_subvector(x,c) case as well

2025-03-21 14:22:49 +00:00

..

AArch64

[MachinePipeliner] Fix incorrect handlings of unpipelineable insts (#126057)

2025-03-21 23:07:41 +09:00

AMDGPU

[AMDGPU] Insert before and after instructions that always use GDS (#131338)

2025-03-21 09:33:04 +00:00

ARC

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ARM

[RemoveDIs] Remove "try-debuginfo-iterators..." test flags (#130298)

2025-03-14 15:50:49 +00:00

AVR

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BPF

[BPF] Fix BitCast Assertion with NonZero AddrSpace (#130722)

2025-03-11 11:23:53 -07:00

CSKY

[CSKY] Update fp16-promote.ll test (NFC)

2025-03-05 12:42:32 +01:00

DirectX

[HLSL] Buffer handle globals should not be constants (#130231)

2025-03-20 11:07:54 -07:00

Generic

[RemoveDIs] Remove "try-debuginfo-iterators..." test flags (#130298)

2025-03-14 15:50:49 +00:00

Hexagon

[llvm][CodeGen] Fix the empty interval issue in Window Scheduler (#129204)

2025-03-17 14:28:47 +08:00

Inputs

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Lanai

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LoongArch

[LoongArch] Fix the type of tls-le symbols (#132324)

2025-03-21 16:05:45 +08:00

M68k

Rename ExpandLargeFpConvertPass to ExpandFpPass (#131128)

2025-03-14 13:11:45 +01:00

Mips

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MIR

[AMDGPU] Allocate scratch space for dVGPRs for CWSR (#130055)

2025-03-19 13:49:19 +01:00

MLRegAlloc

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MSP430

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NVPTX

[NVPTX] Improve 64bit FSH/ROT lowering when shift amount is constant (#131371)

2025-03-18 21:05:00 -07:00

PowerPC

[PowerPC] dmr extract update assembly operand order (#132083)

2025-03-20 13:40:40 -04:00

RISCV

[RISCV] Use vsetvli instead of vlenb in Prologue/Epilogue (#113756)

2025-03-21 17:22:32 +08:00

SPARC

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SPIRV

[SPIR-V] Add support for inline SPIR-V types (#125316)

2025-03-20 15:49:44 -04:00

SystemZ

[SystemZ] Implement i128 funnel shifts

2025-03-15 18:28:44 +01:00

Thumb

[RegAlloc][NewPM] Plug Greedy RA in codegen pipeline (#120557)

2025-03-03 11:06:15 +05:30

Thumb2

[CodeGen] Combine two loops in SlotIndexes.cpp file (#127631)

2025-03-07 08:17:23 +07:00

VE

[NVPTX] Legalize ctpop and ctlz in operation legalization (#130668)

2025-03-12 09:28:40 -07:00

WebAssembly

[WebAssembly] Lower wide SIMD i8 muls (#130785)

2025-03-21 06:57:57 +00:00

WinCFGuard

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WinEH

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X86

[X86] combineConcatVectorOps - add concatenation handling for consecutive extracts of upper subvectors (#132389)

2025-03-21 14:22:49 +00:00

XCore

Reland: [MC] output inlined-at debug info (#106230) (#130306)

2025-03-11 09:43:14 -04:00

Xtensa

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