c5c8040390
This patch introduces per kernel environment. Previously, flags such as execution mode are set through global variables with name like `__kernel_name_exec_mode`. They are accessible on the host by reading the corresponding global variable, but not from the device. Besides, some assumptions, such as no nested parallelism, are not per kernel basis, preventing us applying per kernel optimization in the device runtime. This is a combination and refinement of patch series D116908, D116909, and D116910. Depend on D155886. Reviewed By: jdoerfert Differential Revision: https://reviews.llvm.org/D142569
388 lines
25 KiB
C++
388 lines
25 KiB
C++
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _
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// REQUIRES: amdgpu-registered-target
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// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple x86_64-unknown-unknown -fopenmp-targets=amdgcn-amd-amdhsa -emit-llvm-bc %s -o %t-ppc-host.bc
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// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple amdgcn-amd-amdhsa -fopenmp-targets=amdgcn-amd-amdhsa -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=IR-GPU
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// RUN: %clang_cc1 -verify -triple x86_64-pc-linux-gnu -fopenmp -emit-llvm %s -o - | FileCheck %s --check-prefix=IR
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// Check same results after serialization round-trip
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// RUN: %clang_cc1 -verify -triple x86_64-pc-linux-gnu -fopenmp -emit-pch -o %t %s
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// RUN: %clang_cc1 -verify -triple x86_64-pc-linux-gnu -fopenmp -include-pch %t -emit-llvm %s -o - | FileCheck %s --check-prefix=IR-PCH
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// expected-no-diagnostics
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#ifndef HEADER
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#define HEADER
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typedef void **omp_allocator_handle_t;
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extern const omp_allocator_handle_t omp_null_allocator;
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extern const omp_allocator_handle_t omp_default_mem_alloc;
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extern const omp_allocator_handle_t omp_large_cap_mem_alloc;
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extern const omp_allocator_handle_t omp_const_mem_alloc;
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extern const omp_allocator_handle_t omp_high_bw_mem_alloc;
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extern const omp_allocator_handle_t omp_low_lat_mem_alloc;
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extern const omp_allocator_handle_t omp_cgroup_mem_alloc;
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extern const omp_allocator_handle_t omp_pteam_mem_alloc;
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extern const omp_allocator_handle_t omp_thread_mem_alloc;
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extern int omp_get_thread_num(void);
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#define N 64
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int main() {
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int x = 0;
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int device_result[N] = {0};
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#pragma omp target parallel loop num_threads(N) uses_allocators(omp_pteam_mem_alloc) allocate(omp_pteam_mem_alloc: x) private(x) map(from: device_result)
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for (int i = 0; i < N; i++) {
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x = omp_get_thread_num();
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device_result[i] = i + x;
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}
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}
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#endif
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// IR-GPU-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l37
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// IR-GPU-SAME: (ptr noundef nonnull align 4 dereferenceable(256) [[DEVICE_RESULT:%.*]], ptr noundef [[OMP_PTEAM_MEM_ALLOC:%.*]]) #[[ATTR0:[0-9]+]] {
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// IR-GPU-NEXT: entry:
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// IR-GPU-NEXT: [[DEVICE_RESULT_ADDR:%.*]] = alloca ptr, align 8, addrspace(5)
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// IR-GPU-NEXT: [[OMP_PTEAM_MEM_ALLOC_ADDR:%.*]] = alloca ptr, align 8, addrspace(5)
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// IR-GPU-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [2 x ptr], align 8, addrspace(5)
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// IR-GPU-NEXT: [[DEVICE_RESULT_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DEVICE_RESULT_ADDR]] to ptr
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// IR-GPU-NEXT: [[OMP_PTEAM_MEM_ALLOC_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[OMP_PTEAM_MEM_ALLOC_ADDR]] to ptr
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// IR-GPU-NEXT: [[CAPTURED_VARS_ADDRS_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[CAPTURED_VARS_ADDRS]] to ptr
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// IR-GPU-NEXT: store ptr [[DEVICE_RESULT]], ptr [[DEVICE_RESULT_ADDR_ASCAST]], align 8
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// IR-GPU-NEXT: store ptr [[OMP_PTEAM_MEM_ALLOC]], ptr [[OMP_PTEAM_MEM_ALLOC_ADDR_ASCAST]], align 8
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// IR-GPU-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DEVICE_RESULT_ADDR_ASCAST]], align 8
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// IR-GPU-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr addrspacecast (ptr addrspace(1) @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l37_kernel_environment to ptr))
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// IR-GPU-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
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// IR-GPU-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
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// IR-GPU: user_code.entry:
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// IR-GPU-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(ptr addrspacecast (ptr addrspace(1) @[[GLOB1:[0-9]+]] to ptr))
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// IR-GPU-NEXT: [[TMP3:%.*]] = load ptr, ptr [[OMP_PTEAM_MEM_ALLOC_ADDR_ASCAST]], align 8
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// IR-GPU-NEXT: [[TMP4:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 0, i64 0
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// IR-GPU-NEXT: store ptr [[TMP0]], ptr [[TMP4]], align 8
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// IR-GPU-NEXT: [[TMP5:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 0, i64 1
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// IR-GPU-NEXT: store ptr [[TMP3]], ptr [[TMP5]], align 8
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// IR-GPU-NEXT: call void @__kmpc_parallel_51(ptr addrspacecast (ptr addrspace(1) @[[GLOB1]] to ptr), i32 [[TMP2]], i32 1, i32 64, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l37_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 2)
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// IR-GPU-NEXT: call void @__kmpc_target_deinit()
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// IR-GPU-NEXT: ret void
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// IR-GPU: worker.exit:
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// IR-GPU-NEXT: ret void
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//
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//
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// IR-GPU-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l37_omp_outlined
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// IR-GPU-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(256) [[DEVICE_RESULT:%.*]], ptr noundef [[OMP_PTEAM_MEM_ALLOC:%.*]]) #[[ATTR1:[0-9]+]] {
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// IR-GPU-NEXT: entry:
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// IR-GPU-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8, addrspace(5)
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// IR-GPU-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8, addrspace(5)
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// IR-GPU-NEXT: [[DEVICE_RESULT_ADDR:%.*]] = alloca ptr, align 8, addrspace(5)
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// IR-GPU-NEXT: [[OMP_PTEAM_MEM_ALLOC_ADDR:%.*]] = alloca ptr, align 8, addrspace(5)
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// IR-GPU-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4, addrspace(5)
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// IR-GPU-NEXT: [[TMP:%.*]] = alloca i32, align 4, addrspace(5)
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// IR-GPU-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4, addrspace(5)
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// IR-GPU-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4, addrspace(5)
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// IR-GPU-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4, addrspace(5)
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// IR-GPU-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4, addrspace(5)
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// IR-GPU-NEXT: [[I:%.*]] = alloca i32, align 4, addrspace(5)
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// IR-GPU-NEXT: [[DOTGLOBAL_TID__ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTGLOBAL_TID__ADDR]] to ptr
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// IR-GPU-NEXT: [[DOTBOUND_TID__ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTBOUND_TID__ADDR]] to ptr
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// IR-GPU-NEXT: [[DEVICE_RESULT_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DEVICE_RESULT_ADDR]] to ptr
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// IR-GPU-NEXT: [[OMP_PTEAM_MEM_ALLOC_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[OMP_PTEAM_MEM_ALLOC_ADDR]] to ptr
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// IR-GPU-NEXT: [[DOTOMP_IV_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IV]] to ptr
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// IR-GPU-NEXT: [[TMP_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[TMP]] to ptr
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// IR-GPU-NEXT: [[DOTOMP_LB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_LB]] to ptr
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// IR-GPU-NEXT: [[DOTOMP_UB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_UB]] to ptr
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// IR-GPU-NEXT: [[DOTOMP_STRIDE_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_STRIDE]] to ptr
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// IR-GPU-NEXT: [[DOTOMP_IS_LAST_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IS_LAST]] to ptr
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// IR-GPU-NEXT: [[I_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I]] to ptr
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// IR-GPU-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8
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// IR-GPU-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR_ASCAST]], align 8
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// IR-GPU-NEXT: store ptr [[DEVICE_RESULT]], ptr [[DEVICE_RESULT_ADDR_ASCAST]], align 8
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// IR-GPU-NEXT: store ptr [[OMP_PTEAM_MEM_ALLOC]], ptr [[OMP_PTEAM_MEM_ALLOC_ADDR_ASCAST]], align 8
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// IR-GPU-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DEVICE_RESULT_ADDR_ASCAST]], align 8
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// IR-GPU-NEXT: store i32 0, ptr [[DOTOMP_LB_ASCAST]], align 4
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// IR-GPU-NEXT: store i32 63, ptr [[DOTOMP_UB_ASCAST]], align 4
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// IR-GPU-NEXT: store i32 1, ptr [[DOTOMP_STRIDE_ASCAST]], align 4
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// IR-GPU-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST_ASCAST]], align 4
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// IR-GPU-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8
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// IR-GPU-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
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// IR-GPU-NEXT: call void @__kmpc_for_static_init_4(ptr addrspacecast (ptr addrspace(1) @[[GLOB2:[0-9]+]] to ptr), i32 [[TMP2]], i32 33, ptr [[DOTOMP_IS_LAST_ASCAST]], ptr [[DOTOMP_LB_ASCAST]], ptr [[DOTOMP_UB_ASCAST]], ptr [[DOTOMP_STRIDE_ASCAST]], i32 1, i32 1)
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// IR-GPU-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
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// IR-GPU: omp.dispatch.cond:
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// IR-GPU-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB_ASCAST]], align 4
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// IR-GPU-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 63
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// IR-GPU-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
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// IR-GPU: cond.true:
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// IR-GPU-NEXT: br label [[COND_END:%.*]]
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// IR-GPU: cond.false:
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// IR-GPU-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB_ASCAST]], align 4
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// IR-GPU-NEXT: br label [[COND_END]]
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// IR-GPU: cond.end:
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// IR-GPU-NEXT: [[COND:%.*]] = phi i32 [ 63, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
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// IR-GPU-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB_ASCAST]], align 4
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// IR-GPU-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB_ASCAST]], align 4
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// IR-GPU-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV_ASCAST]], align 4
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// IR-GPU-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4
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// IR-GPU-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB_ASCAST]], align 4
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// IR-GPU-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
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// IR-GPU-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
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// IR-GPU: omp.dispatch.body:
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// IR-GPU-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
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// IR-GPU: omp.inner.for.cond:
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// IR-GPU-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4
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// IR-GPU-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB_ASCAST]], align 4
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// IR-GPU-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
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// IR-GPU-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
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// IR-GPU: omp.inner.for.body:
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// IR-GPU-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4
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// IR-GPU-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
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// IR-GPU-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
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// IR-GPU-NEXT: store i32 [[ADD]], ptr [[I_ASCAST]], align 4
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// IR-GPU-NEXT: [[CALL:%.*]] = call noundef i32 @_Z18omp_get_thread_numv() #[[ATTR5:[0-9]+]]
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// IR-GPU-NEXT: store i32 [[CALL]], ptr addrspacecast (ptr addrspace(3) @x to ptr), align 4
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// IR-GPU-NEXT: [[TMP11:%.*]] = load i32, ptr [[I_ASCAST]], align 4
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// IR-GPU-NEXT: [[TMP12:%.*]] = load i32, ptr addrspacecast (ptr addrspace(3) @x to ptr), align 4
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// IR-GPU-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
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// IR-GPU-NEXT: [[TMP13:%.*]] = load i32, ptr [[I_ASCAST]], align 4
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// IR-GPU-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64
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// IR-GPU-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [64 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM]]
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// IR-GPU-NEXT: store i32 [[ADD3]], ptr [[ARRAYIDX]], align 4
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// IR-GPU-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
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// IR-GPU: omp.body.continue:
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// IR-GPU-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
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// IR-GPU: omp.inner.for.inc:
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// IR-GPU-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4
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// IR-GPU-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP14]], 1
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// IR-GPU-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV_ASCAST]], align 4
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// IR-GPU-NEXT: br label [[OMP_INNER_FOR_COND]]
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// IR-GPU: omp.inner.for.end:
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// IR-GPU-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
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// IR-GPU: omp.dispatch.inc:
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// IR-GPU-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_LB_ASCAST]], align 4
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// IR-GPU-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_STRIDE_ASCAST]], align 4
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// IR-GPU-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], [[TMP16]]
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// IR-GPU-NEXT: store i32 [[ADD5]], ptr [[DOTOMP_LB_ASCAST]], align 4
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// IR-GPU-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB_ASCAST]], align 4
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// IR-GPU-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_STRIDE_ASCAST]], align 4
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// IR-GPU-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP17]], [[TMP18]]
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// IR-GPU-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_UB_ASCAST]], align 4
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// IR-GPU-NEXT: br label [[OMP_DISPATCH_COND]]
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// IR-GPU: omp.dispatch.end:
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// IR-GPU-NEXT: call void @__kmpc_for_static_fini(ptr addrspacecast (ptr addrspace(1) @[[GLOB2]] to ptr), i32 [[TMP2]])
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// IR-GPU-NEXT: ret void
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//
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//
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// IR-LABEL: define {{[^@]+}}@main
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// IR-SAME: () #[[ATTR0:[0-9]+]] {
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// IR-NEXT: entry:
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// IR-NEXT: [[X:%.*]] = alloca i32, align 4
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// IR-NEXT: [[DEVICE_RESULT:%.*]] = alloca [64 x i32], align 16
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// IR-NEXT: store i32 0, ptr [[X]], align 4
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// IR-NEXT: call void @llvm.memset.p0.i64(ptr align 16 [[DEVICE_RESULT]], i8 0, i64 256, i1 false)
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// IR-NEXT: [[TMP0:%.*]] = load ptr, ptr @omp_pteam_mem_alloc, align 8
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// IR-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l37(ptr [[DEVICE_RESULT]], ptr [[TMP0]]) #[[ATTR3:[0-9]+]]
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// IR-NEXT: ret i32 0
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//
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//
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// IR-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l37
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// IR-SAME: (ptr noundef nonnull align 4 dereferenceable(256) [[DEVICE_RESULT:%.*]], ptr noundef [[OMP_PTEAM_MEM_ALLOC:%.*]]) #[[ATTR2:[0-9]+]] {
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// IR-NEXT: entry:
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// IR-NEXT: [[DEVICE_RESULT_ADDR:%.*]] = alloca ptr, align 8
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// IR-NEXT: [[OMP_PTEAM_MEM_ALLOC_ADDR:%.*]] = alloca ptr, align 8
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// IR-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2:[0-9]+]])
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// IR-NEXT: store ptr [[DEVICE_RESULT]], ptr [[DEVICE_RESULT_ADDR]], align 8
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// IR-NEXT: store ptr [[OMP_PTEAM_MEM_ALLOC]], ptr [[OMP_PTEAM_MEM_ALLOC_ADDR]], align 8
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// IR-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DEVICE_RESULT_ADDR]], align 8
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// IR-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB2]], i32 [[TMP0]], i32 64)
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// IR-NEXT: [[TMP2:%.*]] = load ptr, ptr [[OMP_PTEAM_MEM_ALLOC_ADDR]], align 8
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// IR-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l37.omp_outlined, ptr [[TMP1]], ptr [[TMP2]])
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// IR-NEXT: ret void
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//
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//
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// IR-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l37.omp_outlined
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// IR-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(256) [[DEVICE_RESULT:%.*]], ptr noundef [[OMP_PTEAM_MEM_ALLOC:%.*]]) #[[ATTR2]] {
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// IR-NEXT: entry:
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// IR-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
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// IR-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
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// IR-NEXT: [[DEVICE_RESULT_ADDR:%.*]] = alloca ptr, align 8
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// IR-NEXT: [[OMP_PTEAM_MEM_ALLOC_ADDR:%.*]] = alloca ptr, align 8
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// IR-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
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// IR-NEXT: [[TMP:%.*]] = alloca i32, align 4
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// IR-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
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// IR-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
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// IR-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
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// IR-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
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// IR-NEXT: [[I:%.*]] = alloca i32, align 4
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// IR-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
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// IR-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
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// IR-NEXT: store ptr [[DEVICE_RESULT]], ptr [[DEVICE_RESULT_ADDR]], align 8
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// IR-NEXT: store ptr [[OMP_PTEAM_MEM_ALLOC]], ptr [[OMP_PTEAM_MEM_ALLOC_ADDR]], align 8
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// IR-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DEVICE_RESULT_ADDR]], align 8
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// IR-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
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// IR-NEXT: store i32 63, ptr [[DOTOMP_UB]], align 4
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// IR-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
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// IR-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
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// IR-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
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// IR-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
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// IR-NEXT: [[TMP3:%.*]] = load ptr, ptr @omp_pteam_mem_alloc, align 8
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// IR-NEXT: [[DOTX__VOID_ADDR:%.*]] = call ptr @__kmpc_alloc(i32 [[TMP2]], i64 4, ptr [[TMP3]])
|
|
// IR-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP2]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
|
|
// IR-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
|
|
// IR-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 63
|
|
// IR-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// IR: cond.true:
|
|
// IR-NEXT: br label [[COND_END:%.*]]
|
|
// IR: cond.false:
|
|
// IR-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
|
|
// IR-NEXT: br label [[COND_END]]
|
|
// IR: cond.end:
|
|
// IR-NEXT: [[COND:%.*]] = phi i32 [ 63, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
|
|
// IR-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
|
|
// IR-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
|
|
// IR-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4
|
|
// IR-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// IR: omp.inner.for.cond:
|
|
// IR-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
|
|
// IR-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
|
|
// IR-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
|
|
// IR-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
|
|
// IR: omp.inner.for.cond.cleanup:
|
|
// IR-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
|
|
// IR: omp.inner.for.body:
|
|
// IR-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
|
|
// IR-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
|
|
// IR-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
|
|
// IR-NEXT: store i32 [[ADD]], ptr [[I]], align 4
|
|
// IR-NEXT: [[CALL:%.*]] = call noundef i32 @_Z18omp_get_thread_numv()
|
|
// IR-NEXT: store i32 [[CALL]], ptr [[DOTX__VOID_ADDR]], align 4
|
|
// IR-NEXT: [[TMP10:%.*]] = load i32, ptr [[I]], align 4
|
|
// IR-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTX__VOID_ADDR]], align 4
|
|
// IR-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], [[TMP11]]
|
|
// IR-NEXT: [[TMP12:%.*]] = load i32, ptr [[I]], align 4
|
|
// IR-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP12]] to i64
|
|
// IR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [64 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM]]
|
|
// IR-NEXT: store i32 [[ADD2]], ptr [[ARRAYIDX]], align 4
|
|
// IR-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// IR: omp.body.continue:
|
|
// IR-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// IR: omp.inner.for.inc:
|
|
// IR-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
|
|
// IR-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP13]], 1
|
|
// IR-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4
|
|
// IR-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// IR: omp.inner.for.end:
|
|
// IR-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// IR: omp.loop.exit:
|
|
// IR-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]])
|
|
// IR-NEXT: [[TMP14:%.*]] = load ptr, ptr @omp_pteam_mem_alloc, align 8
|
|
// IR-NEXT: call void @__kmpc_free(i32 [[TMP2]], ptr [[DOTX__VOID_ADDR]], ptr [[TMP14]])
|
|
// IR-NEXT: ret void
|
|
//
|
|
//
|
|
// IR-PCH-LABEL: define {{[^@]+}}@main
|
|
// IR-PCH-SAME: () #[[ATTR0:[0-9]+]] {
|
|
// IR-PCH-NEXT: entry:
|
|
// IR-PCH-NEXT: [[X:%.*]] = alloca i32, align 4
|
|
// IR-PCH-NEXT: [[DEVICE_RESULT:%.*]] = alloca [64 x i32], align 16
|
|
// IR-PCH-NEXT: store i32 0, ptr [[X]], align 4
|
|
// IR-PCH-NEXT: call void @llvm.memset.p0.i64(ptr align 16 [[DEVICE_RESULT]], i8 0, i64 256, i1 false)
|
|
// IR-PCH-NEXT: [[TMP0:%.*]] = load ptr, ptr @omp_pteam_mem_alloc, align 8
|
|
// IR-PCH-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l37(ptr [[DEVICE_RESULT]], ptr [[TMP0]]) #[[ATTR3:[0-9]+]]
|
|
// IR-PCH-NEXT: ret i32 0
|
|
//
|
|
//
|
|
// IR-PCH-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l37
|
|
// IR-PCH-SAME: (ptr noundef nonnull align 4 dereferenceable(256) [[DEVICE_RESULT:%.*]], ptr noundef [[OMP_PTEAM_MEM_ALLOC:%.*]]) #[[ATTR2:[0-9]+]] {
|
|
// IR-PCH-NEXT: entry:
|
|
// IR-PCH-NEXT: [[DEVICE_RESULT_ADDR:%.*]] = alloca ptr, align 8
|
|
// IR-PCH-NEXT: [[OMP_PTEAM_MEM_ALLOC_ADDR:%.*]] = alloca ptr, align 8
|
|
// IR-PCH-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2:[0-9]+]])
|
|
// IR-PCH-NEXT: store ptr [[DEVICE_RESULT]], ptr [[DEVICE_RESULT_ADDR]], align 8
|
|
// IR-PCH-NEXT: store ptr [[OMP_PTEAM_MEM_ALLOC]], ptr [[OMP_PTEAM_MEM_ALLOC_ADDR]], align 8
|
|
// IR-PCH-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DEVICE_RESULT_ADDR]], align 8
|
|
// IR-PCH-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB2]], i32 [[TMP0]], i32 64)
|
|
// IR-PCH-NEXT: [[TMP2:%.*]] = load ptr, ptr [[OMP_PTEAM_MEM_ALLOC_ADDR]], align 8
|
|
// IR-PCH-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l37.omp_outlined, ptr [[TMP1]], ptr [[TMP2]])
|
|
// IR-PCH-NEXT: ret void
|
|
//
|
|
//
|
|
// IR-PCH-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l37.omp_outlined
|
|
// IR-PCH-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(256) [[DEVICE_RESULT:%.*]], ptr noundef [[OMP_PTEAM_MEM_ALLOC:%.*]]) #[[ATTR2]] {
|
|
// IR-PCH-NEXT: entry:
|
|
// IR-PCH-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
// IR-PCH-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
// IR-PCH-NEXT: [[DEVICE_RESULT_ADDR:%.*]] = alloca ptr, align 8
|
|
// IR-PCH-NEXT: [[OMP_PTEAM_MEM_ALLOC_ADDR:%.*]] = alloca ptr, align 8
|
|
// IR-PCH-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// IR-PCH-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// IR-PCH-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// IR-PCH-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// IR-PCH-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// IR-PCH-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// IR-PCH-NEXT: [[I:%.*]] = alloca i32, align 4
|
|
// IR-PCH-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// IR-PCH-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
|
|
// IR-PCH-NEXT: store ptr [[DEVICE_RESULT]], ptr [[DEVICE_RESULT_ADDR]], align 8
|
|
// IR-PCH-NEXT: store ptr [[OMP_PTEAM_MEM_ALLOC]], ptr [[OMP_PTEAM_MEM_ALLOC_ADDR]], align 8
|
|
// IR-PCH-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DEVICE_RESULT_ADDR]], align 8
|
|
// IR-PCH-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
|
|
// IR-PCH-NEXT: store i32 63, ptr [[DOTOMP_UB]], align 4
|
|
// IR-PCH-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
|
|
// IR-PCH-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
|
|
// IR-PCH-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// IR-PCH-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
|
|
// IR-PCH-NEXT: [[TMP3:%.*]] = load ptr, ptr @omp_pteam_mem_alloc, align 8
|
|
// IR-PCH-NEXT: [[DOTX__VOID_ADDR:%.*]] = call ptr @__kmpc_alloc(i32 [[TMP2]], i64 4, ptr [[TMP3]])
|
|
// IR-PCH-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP2]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
|
|
// IR-PCH-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
|
|
// IR-PCH-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 63
|
|
// IR-PCH-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// IR-PCH: cond.true:
|
|
// IR-PCH-NEXT: br label [[COND_END:%.*]]
|
|
// IR-PCH: cond.false:
|
|
// IR-PCH-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
|
|
// IR-PCH-NEXT: br label [[COND_END]]
|
|
// IR-PCH: cond.end:
|
|
// IR-PCH-NEXT: [[COND:%.*]] = phi i32 [ 63, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
|
|
// IR-PCH-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
|
|
// IR-PCH-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
|
|
// IR-PCH-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4
|
|
// IR-PCH-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// IR-PCH: omp.inner.for.cond:
|
|
// IR-PCH-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
|
|
// IR-PCH-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
|
|
// IR-PCH-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
|
|
// IR-PCH-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
|
|
// IR-PCH: omp.inner.for.cond.cleanup:
|
|
// IR-PCH-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
|
|
// IR-PCH: omp.inner.for.body:
|
|
// IR-PCH-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
|
|
// IR-PCH-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
|
|
// IR-PCH-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
|
|
// IR-PCH-NEXT: store i32 [[ADD]], ptr [[I]], align 4
|
|
// IR-PCH-NEXT: [[CALL:%.*]] = call noundef i32 @_Z18omp_get_thread_numv()
|
|
// IR-PCH-NEXT: store i32 [[CALL]], ptr [[DOTX__VOID_ADDR]], align 4
|
|
// IR-PCH-NEXT: [[TMP10:%.*]] = load i32, ptr [[I]], align 4
|
|
// IR-PCH-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTX__VOID_ADDR]], align 4
|
|
// IR-PCH-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], [[TMP11]]
|
|
// IR-PCH-NEXT: [[TMP12:%.*]] = load i32, ptr [[I]], align 4
|
|
// IR-PCH-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP12]] to i64
|
|
// IR-PCH-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [64 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM]]
|
|
// IR-PCH-NEXT: store i32 [[ADD2]], ptr [[ARRAYIDX]], align 4
|
|
// IR-PCH-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// IR-PCH: omp.body.continue:
|
|
// IR-PCH-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// IR-PCH: omp.inner.for.inc:
|
|
// IR-PCH-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
|
|
// IR-PCH-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP13]], 1
|
|
// IR-PCH-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4
|
|
// IR-PCH-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// IR-PCH: omp.inner.for.end:
|
|
// IR-PCH-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// IR-PCH: omp.loop.exit:
|
|
// IR-PCH-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]])
|
|
// IR-PCH-NEXT: [[TMP14:%.*]] = load ptr, ptr @omp_pteam_mem_alloc, align 8
|
|
// IR-PCH-NEXT: call void @__kmpc_free(i32 [[TMP2]], ptr [[DOTX__VOID_ADDR]], ptr [[TMP14]])
|
|
// IR-PCH-NEXT: ret void
|
|
//
|