c88719483c
These statements are like switch statements in C, but without the 'case' keyword in labels. How labels are parsed. In UnwrappedLineParser, the program tries to parse a statement every time it sees a colon. In TokenAnnotator, a colon that isn't part of an expression is annotated as a label. The token type `TT_GotoLabelColon` is added. We did not include Verilog in the name because we thought we would eventually have to fix the problem that case labels in C can't contain ternary conditional expressions and we would use that token type. The style is like below. Labels are on separate lines and indented by default. The linked style guide also has examples where labels and the corresponding statements are on the same lines. They are not supported for now. https://github.com/lowRISC/style-guides/blob/master/VerilogCodingStyle.md ``` case (state_q) StIdle: state_d = StA; StA: begin state_d = StB; end endcase ``` Differential Revision: https://reviews.llvm.org/D128714
571 lines
17 KiB
C++
571 lines
17 KiB
C++
//===- unittest/Format/FormatTestVerilog.cpp ------------------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include "FormatTestUtils.h"
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#include "clang/Format/Format.h"
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#include "llvm/Support/Debug.h"
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#include "gtest/gtest.h"
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#define DEBUG_TYPE "format-test"
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namespace clang {
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namespace format {
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class FormatTestVerilog : public ::testing::Test {
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protected:
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static std::string format(llvm::StringRef Code, unsigned Offset,
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unsigned Length, const FormatStyle &Style) {
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LLVM_DEBUG(llvm::errs() << "---\n");
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LLVM_DEBUG(llvm::errs() << Code << "\n\n");
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std::vector<tooling::Range> Ranges(1, tooling::Range(Offset, Length));
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tooling::Replacements Replaces = reformat(Style, Code, Ranges);
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auto Result = applyAllReplacements(Code, Replaces);
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EXPECT_TRUE(static_cast<bool>(Result));
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LLVM_DEBUG(llvm::errs() << "\n" << *Result << "\n\n");
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return *Result;
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}
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static std::string
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format(llvm::StringRef Code,
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const FormatStyle &Style = getLLVMStyle(FormatStyle::LK_Verilog)) {
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return format(Code, 0, Code.size(), Style);
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}
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static void verifyFormat(
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llvm::StringRef Code,
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const FormatStyle &Style = getLLVMStyle(FormatStyle::LK_Verilog)) {
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EXPECT_EQ(Code.str(), format(Code, Style)) << "Expected code is not stable";
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EXPECT_EQ(Code.str(),
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format(test::messUp(Code, /*HandleHash=*/false), Style));
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}
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};
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TEST_F(FormatTestVerilog, BasedLiteral) {
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verifyFormat("x = '0;");
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verifyFormat("x = '1;");
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verifyFormat("x = 'X;");
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verifyFormat("x = 'x;");
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verifyFormat("x = 'Z;");
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verifyFormat("x = 'z;");
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verifyFormat("x = 659;");
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verifyFormat("x = 'h837ff;");
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verifyFormat("x = 'o7460;");
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verifyFormat("x = 4'b1001;");
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verifyFormat("x = 5'D3;");
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verifyFormat("x = 3'b01x;");
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verifyFormat("x = 12'hx;");
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verifyFormat("x = 16'hz;");
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verifyFormat("x = -8'd6;");
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verifyFormat("x = 4'shf;");
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verifyFormat("x = -4'sd15;");
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verifyFormat("x = 16'sd?;");
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}
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TEST_F(FormatTestVerilog, Block) {
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verifyFormat("begin\n"
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" x = x;\n"
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"end");
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verifyFormat("begin : x\n"
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" x = x;\n"
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"end : x");
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verifyFormat("begin\n"
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" x = x;\n"
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" x = x;\n"
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"end");
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verifyFormat("fork\n"
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" x = x;\n"
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"join");
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verifyFormat("fork\n"
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" x = x;\n"
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"join_any");
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verifyFormat("fork\n"
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" x = x;\n"
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"join_none");
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verifyFormat("generate\n"
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" x = x;\n"
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"endgenerate");
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verifyFormat("generate : x\n"
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" x = x;\n"
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"endgenerate : x");
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// Nested blocks.
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verifyFormat("begin\n"
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" begin\n"
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" end\n"
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"end");
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verifyFormat("begin : x\n"
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" begin\n"
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" end\n"
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"end : x");
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verifyFormat("begin : x\n"
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" begin : x\n"
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" end : x\n"
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"end : x");
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verifyFormat("begin\n"
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" begin : x\n"
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" end : x\n"
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"end");
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// Test that 'disable fork' and 'rand join' don't get mistaken as blocks.
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verifyFormat("disable fork;\n"
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"x = x;");
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verifyFormat("rand join x x;\n"
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"x = x;");
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}
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TEST_F(FormatTestVerilog, Case) {
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verifyFormat("case (data)\n"
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"endcase");
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verifyFormat("casex (data)\n"
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"endcase");
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verifyFormat("casez (data)\n"
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"endcase");
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verifyFormat("case (data) inside\n"
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"endcase");
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verifyFormat("case (data)\n"
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" 16'd0:\n"
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" result = 10'b0111111111;\n"
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"endcase");
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verifyFormat("case (data)\n"
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" xxxxxxxx:\n"
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" result = 10'b0111111111;\n"
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"endcase");
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// Test labels with multiple options.
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verifyFormat("case (data)\n"
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" 16'd0, 16'd1:\n"
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" result = 10'b0111111111;\n"
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"endcase");
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verifyFormat("case (data)\n"
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" 16'd0, //\n"
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" 16'd1:\n"
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" result = 10'b0111111111;\n"
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"endcase");
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// Test that blocks following labels are indented.
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verifyFormat("case (data)\n"
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" 16'd1: fork\n"
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" result = 10'b1011111111;\n"
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" join\n"
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"endcase\n");
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verifyFormat("case (data)\n"
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" 16'd1: fork : x\n"
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" result = 10'b1011111111;\n"
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" join : x\n"
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"endcase\n");
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// Test default.
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verifyFormat("case (data)\n"
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" default\n"
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" result = 10'b1011111111;\n"
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"endcase");
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verifyFormat("case (data)\n"
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" default:\n"
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" result = 10'b1011111111;\n"
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"endcase");
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// Test that question marks and colons don't get mistaken as labels.
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verifyFormat("case (data)\n"
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" 8'b1???????:\n"
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" instruction1(ir);\n"
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"endcase");
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verifyFormat("case (data)\n"
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" x ? 8'b1??????? : 1:\n"
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" instruction3(ir);\n"
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"endcase");
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// Test indention options.
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auto Style = getLLVMStyle(FormatStyle::LK_Verilog);
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Style.IndentCaseLabels = false;
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verifyFormat("case (data)\n"
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"16'd0:\n"
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" result = 10'b0111111111;\n"
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"endcase",
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Style);
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verifyFormat("case (data)\n"
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"16'd0: begin\n"
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" result = 10'b0111111111;\n"
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"end\n"
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"endcase",
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Style);
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Style.IndentCaseLabels = true;
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verifyFormat("case (data)\n"
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" 16'd0:\n"
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" result = 10'b0111111111;\n"
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"endcase",
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Style);
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verifyFormat("case (data)\n"
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" 16'd0: begin\n"
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" result = 10'b0111111111;\n"
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" end\n"
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"endcase",
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Style);
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}
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TEST_F(FormatTestVerilog, Delay) {
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// Delay by the default unit.
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verifyFormat("#0;");
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verifyFormat("#1;");
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verifyFormat("#10;");
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verifyFormat("#1.5;");
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// Explicit unit.
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verifyFormat("#1fs;");
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verifyFormat("#1.5fs;");
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verifyFormat("#1ns;");
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verifyFormat("#1.5ns;");
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verifyFormat("#1us;");
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verifyFormat("#1.5us;");
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verifyFormat("#1ms;");
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verifyFormat("#1.5ms;");
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verifyFormat("#1s;");
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verifyFormat("#1.5s;");
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// The following expression should be on the same line.
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verifyFormat("#1 x = x;");
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EXPECT_EQ("#1 x = x;", format("#1\n"
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"x = x;"));
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}
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TEST_F(FormatTestVerilog, Hierarchy) {
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verifyFormat("module x;\n"
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"endmodule");
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// Test that the end label is on the same line as the end keyword.
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verifyFormat("module x;\n"
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"endmodule : x");
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// Test that things inside are indented.
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verifyFormat("module x;\n"
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" generate\n"
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" endgenerate\n"
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"endmodule");
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verifyFormat("program x;\n"
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" generate\n"
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" endgenerate\n"
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"endprogram");
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verifyFormat("interface x;\n"
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" generate\n"
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" endgenerate\n"
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"endinterface");
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verifyFormat("task x;\n"
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" generate\n"
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" endgenerate\n"
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"endtask");
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verifyFormat("function x;\n"
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" generate\n"
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" endgenerate\n"
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"endfunction");
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verifyFormat("class x;\n"
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" generate\n"
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" endgenerate\n"
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"endclass");
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// Test that they nest.
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verifyFormat("module x;\n"
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" program x;\n"
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" program x;\n"
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" endprogram\n"
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" endprogram\n"
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"endmodule");
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// Test that an extern declaration doesn't change the indentation.
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verifyFormat("extern module x;\n"
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"x = x;");
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// Test complex headers
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verifyFormat("extern module x\n"
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" import x.x::x::*;\n"
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" import x;\n"
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" #(parameter x)\n"
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" (output x);");
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verifyFormat("module x\n"
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" import x.x::x::*;\n"
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" import x;\n"
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" #(parameter x)\n"
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" (output x);\n"
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" generate\n"
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" endgenerate\n"
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"endmodule : x");
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verifyFormat("virtual class x\n"
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" (x)\n"
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" extends x(x)\n"
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" implements x, x, x;\n"
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" generate\n"
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" endgenerate\n"
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"endclass : x\n");
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verifyFormat("function automatic logic [1 : 0] x\n"
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" (input x);\n"
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" generate\n"
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" endgenerate\n"
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"endfunction : x");
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}
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TEST_F(FormatTestVerilog, If) {
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verifyFormat("if (x)\n"
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" x = x;");
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verifyFormat("if (x)\n"
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" x = x;\n"
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"x = x;");
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// Test else
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verifyFormat("if (x)\n"
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" x = x;\n"
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"else if (x)\n"
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" x = x;\n"
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"else\n"
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" x = x;");
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verifyFormat("if (x) begin\n"
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" x = x;\n"
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"end else if (x) begin\n"
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" x = x;\n"
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"end else begin\n"
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" x = x;\n"
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"end");
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verifyFormat("if (x) begin : x\n"
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" x = x;\n"
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"end : x else if (x) begin : x\n"
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" x = x;\n"
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"end : x else begin : x\n"
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" x = x;\n"
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"end : x");
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// Test block keywords.
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verifyFormat("if (x) begin\n"
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" x = x;\n"
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"end");
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verifyFormat("if (x) begin : x\n"
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" x = x;\n"
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"end : x");
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verifyFormat("if (x) begin\n"
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" x = x;\n"
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" x = x;\n"
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"end");
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verifyFormat("if (x) fork\n"
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" x = x;\n"
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"join");
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verifyFormat("if (x) fork\n"
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" x = x;\n"
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"join_any");
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verifyFormat("if (x) fork\n"
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" x = x;\n"
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"join_none");
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verifyFormat("if (x) generate\n"
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" x = x;\n"
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"endgenerate");
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verifyFormat("if (x) generate : x\n"
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" x = x;\n"
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"endgenerate : x");
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// Test that concatenation braces don't get regarded as blocks.
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verifyFormat("if (x)\n"
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" {x} = x;");
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verifyFormat("if (x)\n"
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" x = {x};");
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verifyFormat("if (x)\n"
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" x = {x};\n"
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"else\n"
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" {x} = {x};");
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}
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TEST_F(FormatTestVerilog, Operators) {
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// Test that unary operators are not followed by space.
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verifyFormat("x = +x;");
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verifyFormat("x = -x;");
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verifyFormat("x = !x;");
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verifyFormat("x = ~x;");
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verifyFormat("x = &x;");
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verifyFormat("x = ~&x;");
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verifyFormat("x = |x;");
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verifyFormat("x = ~|x;");
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verifyFormat("x = ^x;");
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verifyFormat("x = ~^x;");
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verifyFormat("x = ^~x;");
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verifyFormat("x = ++x;");
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verifyFormat("x = --x;");
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// Test that operators don't get split.
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verifyFormat("x = x++;");
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verifyFormat("x = x--;");
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verifyFormat("x = x ** x;");
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verifyFormat("x = x << x;");
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verifyFormat("x = x >> x;");
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verifyFormat("x = x <<< x;");
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verifyFormat("x = x >>> x;");
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verifyFormat("x = x <= x;");
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verifyFormat("x = x >= x;");
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verifyFormat("x = x == x;");
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verifyFormat("x = x != x;");
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verifyFormat("x = x === x;");
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verifyFormat("x = x !== x;");
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verifyFormat("x = x ==? x;");
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verifyFormat("x = x !=? x;");
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verifyFormat("x = x ~^ x;");
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verifyFormat("x = x ^~ x;");
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verifyFormat("x = x && x;");
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verifyFormat("x = x || x;");
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verifyFormat("x = x->x;");
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verifyFormat("x = x <-> x;");
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verifyFormat("x += x;");
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verifyFormat("x -= x;");
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verifyFormat("x *= x;");
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verifyFormat("x /= x;");
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verifyFormat("x %= x;");
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verifyFormat("x &= x;");
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verifyFormat("x ^= x;");
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verifyFormat("x |= x;");
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verifyFormat("x <<= x;");
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verifyFormat("x >>= x;");
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verifyFormat("x <<<= x;");
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verifyFormat("x >>>= x;");
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verifyFormat("x <= x;");
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// Test that space is added between operators.
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EXPECT_EQ("x = x < -x;", format("x=x<-x;"));
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EXPECT_EQ("x = x << -x;", format("x=x<<-x;"));
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EXPECT_EQ("x = x <<< -x;", format("x=x<<<-x;"));
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}
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TEST_F(FormatTestVerilog, Preprocessor) {
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auto Style = getLLVMStyle(FormatStyle::LK_Verilog);
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Style.ColumnLimit = 20;
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// Macro definitions.
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EXPECT_EQ("`define X \\\n"
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" if (x) \\\n"
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" x = x;",
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format("`define X if(x)x=x;", Style));
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EXPECT_EQ("`define X(x) \\\n"
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" if (x) \\\n"
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" x = x;",
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format("`define X(x) if(x)x=x;", Style));
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EXPECT_EQ("`define X \\\n"
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" x = x; \\\n"
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" x = x;",
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format("`define X x=x;x=x;", Style));
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// Macro definitions with invocations inside.
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EXPECT_EQ("`define LIST \\\n"
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" `ENTRY \\\n"
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" `ENTRY",
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format("`define LIST \\\n"
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"`ENTRY \\\n"
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"`ENTRY",
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Style));
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EXPECT_EQ("`define LIST \\\n"
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" `x = `x; \\\n"
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" `x = `x;",
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format("`define LIST \\\n"
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"`x = `x; \\\n"
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"`x = `x;",
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Style));
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EXPECT_EQ("`define LIST \\\n"
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" `x = `x; \\\n"
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" `x = `x;",
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format("`define LIST `x=`x;`x=`x;", Style));
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// Macro invocations.
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verifyFormat("`x = (`x1 + `x2 + x);");
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// Lines starting with a preprocessor directive should not be indented.
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std::string Directives[] = {
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"begin_keywords",
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"celldefine",
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"default_nettype",
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"define",
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"else",
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"elsif",
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"end_keywords",
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"endcelldefine",
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"endif",
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"ifdef",
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"ifndef",
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"include",
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"line",
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"nounconnected_drive",
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"pragma",
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"resetall",
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"timescale",
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"unconnected_drive",
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"undef",
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"undefineall",
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};
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for (auto &Name : Directives) {
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EXPECT_EQ("if (x)\n"
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"`" +
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Name +
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"\n"
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" ;",
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format("if (x)\n"
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"`" +
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Name +
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"\n"
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";",
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Style));
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}
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// Lines starting with a regular macro invocation should be indented as a
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// normal line.
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EXPECT_EQ("if (x)\n"
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" `x = `x;\n"
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"`timescale 1ns / 1ps",
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format("if (x)\n"
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"`x = `x;\n"
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"`timescale 1ns / 1ps",
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Style));
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EXPECT_EQ("if (x)\n"
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"`timescale 1ns / 1ps\n"
|
|
" `x = `x;",
|
|
format("if (x)\n"
|
|
"`timescale 1ns / 1ps\n"
|
|
"`x = `x;",
|
|
Style));
|
|
std::string NonDirectives[] = {
|
|
// For `__FILE__` and `__LINE__`, although the standard classifies them as
|
|
// preprocessor directives, they are used like regular macros.
|
|
"__FILE__", "__LINE__", "elif", "foo", "x",
|
|
};
|
|
for (auto &Name : NonDirectives) {
|
|
EXPECT_EQ("if (x)\n"
|
|
" `" +
|
|
Name + ";",
|
|
format("if (x)\n"
|
|
"`" +
|
|
Name +
|
|
"\n"
|
|
";",
|
|
Style));
|
|
}
|
|
}
|
|
|
|
TEST_F(FormatTestVerilog, Primitive) {
|
|
verifyFormat("primitive multiplexer\n"
|
|
" (mux, control, dataA, dataB);\n"
|
|
" output mux;\n"
|
|
" input control, dataA, dataB;\n"
|
|
" table\n"
|
|
" 0 1 ? : 1;\n"
|
|
" 0 0 ? : 0;\n"
|
|
" 1 ? 1 : 1;\n"
|
|
" 1 ? 0 : 0;\n"
|
|
" x 0 0 : 0;\n"
|
|
" x 1 1 : 1;\n"
|
|
" endtable\n"
|
|
"endprimitive");
|
|
verifyFormat("primitive latch\n"
|
|
" (q, ena_, data);\n"
|
|
" output q;\n"
|
|
" reg q;\n"
|
|
" input ena_, data;\n"
|
|
" table\n"
|
|
" 0 1 : ? : 1;\n"
|
|
" 0 0 : ? : 0;\n"
|
|
" 1 ? : ? : -;\n"
|
|
" ? * : ? : -;\n"
|
|
" endtable\n"
|
|
"endprimitive");
|
|
verifyFormat("primitive d\n"
|
|
" (q, clock, data);\n"
|
|
" output q;\n"
|
|
" reg q;\n"
|
|
" input clock, data;\n"
|
|
" table\n"
|
|
" (01) 0 : ? : 0;\n"
|
|
" (01) 1 : ? : 1;\n"
|
|
" (0?) 1 : 1 : 1;\n"
|
|
" (0?) 0 : 0 : 0;\n"
|
|
" (?0) ? : ? : -;\n"
|
|
" (?\?) ? : ? : -;\n"
|
|
" endtable\n"
|
|
"endprimitive");
|
|
}
|
|
} // namespace format
|
|
} // end namespace clang
|