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llvm-project/llvm/test/CodeGen
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Simon Pilgrim c8dfd0008b [PowerPC] Regenerate optcmp.ll test checks to fix issue reported on D77354
2020-04-08 18:00:43 +01:00
..
AArch64
[AARCH64][GISEL] arm64-fallback.ll - Refresh remarks to fix issue reported on D77354
2020-04-08 15:28:54 +01:00
AMDGPU
[AMDGPU] Refresh fmin_legacy.ll checks to fix issue reported on D77354
2020-04-08 17:05:29 +01:00
ARC
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ARM
[ARM] Fix thumb1_return_sequence typo in check to fix issue reported on D77354
2020-04-08 16:00:45 +01:00
AVR
[AVR] Generalize the previous interrupt bugfix to signal handlers too
2020-03-31 19:33:34 +13:00
BPF
[llvm] Fix missing FileCheck directive colons
2020-04-06 09:59:08 -06:00
Generic
Add MIR-level debugify with only locations support for now
2020-04-07 16:25:13 -07:00
Hexagon
[llvm] Fix missing FileCheck directive colons
2020-04-06 09:59:08 -06:00
Inputs
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Lanai
Revert "Revert "Reland "[Support] make report_fatal_error abort instead of exit"""
2020-02-13 10:16:06 -08:00
Mips
[llvm] Fix missing FileCheck directive colons
2020-04-06 09:59:08 -06:00
MIR
AMDGPU: Assume f32 denormals are enabled by default
2020-04-02 17:17:12 -04:00
MSP430
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NVPTX
[llvm] Fix missing FileCheck directive colons
2020-04-06 09:59:08 -06:00
PowerPC
[PowerPC] Regenerate optcmp.ll test checks to fix issue reported on D77354
2020-04-08 18:00:43 +01:00
RISCV
[LegalizeTypes][RISCV] Correctly sign-extend comparison for ATOMIC_CMP_XCHG
2020-04-01 15:51:26 +01:00
SPARC
[Sparc] Fix incorrect operand for matching CMPri pattern
2020-03-02 11:36:32 +08:00
SystemZ
[LoopDataPrefetch + SystemZ] Let target decide on prefetching for each loop.
2020-04-02 14:57:46 +02:00
Thumb
[ARM] unwinding .pad instructions missing in execute-only prologue
2020-04-07 11:51:59 +01:00
Thumb2
[ARM][MVE] Optimise offset addresses of gathers/scatters
2020-04-08 11:46:57 +01:00
VE
[VE] Update lea/load/store instructions
2020-04-06 11:49:46 +02:00
WebAssembly
[WebAssembly] EmscriptenEHSjLj: Mark more functions as imported
2020-04-06 21:27:31 -07:00
WinCFGuard
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WinEH
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X86
[X86][SSE] Combine PTEST(AND(X,Y),AND(X,Y)) -> PTEST(X,Y) and ANDN equivalents
2020-04-08 12:42:22 +01:00
XCore
[XCore] Add instruction pattern for bitrev
2020-02-21 09:28:49 +08:00