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llvm-project/llvm/test/CodeGen
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Guillaume Chatelet ca11c480e7 [Alignment][NFC] Convert MachineIRBuilder::buildDynStackAlloc to Align 
Summary:
The change in IRTranslator is not trivial but is NFC as far as I can tell.

This is patch is part of a series to introduce an Alignment type.
See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html
See this patch for the introduction of the type: https://reviews.llvm.org/D64790

Reviewers: courbet

Subscribers: hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D77292
2020-04-03 09:05:19 +00:00
..
AArch64
[Alignment][NFC] Convert MachineIRBuilder::buildDynStackAlloc to Align
2020-04-03 09:05:19 +00:00
AMDGPU
[AMDGPU] Handle SMRD signed offset immediate
2020-04-02 17:41:52 -07:00
ARC
…
ARM
[ARM] Fix qdadd operand order
2020-03-31 10:11:36 +01:00
AVR
[AVR] Generalize the previous interrupt bugfix to signal handlers too
2020-03-31 19:33:34 +13:00
BPF
[BPF] support 128bit int explicitly in layout spec
2020-03-28 11:46:29 -07:00
Generic
[X86] Move combineLoopMAddPattern and combineLoopSADPattern to an IR pass before SelecitonDAG.
2020-03-26 14:10:20 -07:00
Hexagon
Revert "Include static prof data when collecting loop BBs"
2020-03-24 09:41:16 -07:00
Inputs
…
Lanai
Revert "Revert "Reland "[Support] make report_fatal_error abort instead of exit"""
2020-02-13 10:16:06 -08:00
Mips
[Mips] Make MipsBranchExpansion aware of BBIT family of branch
2020-03-31 09:20:51 +02:00
MIR
AMDGPU: Assume f32 denormals are enabled by default
2020-04-02 17:17:12 -04:00
MSP430
…
NVPTX
[DAGCombiner] Require ninf for sqrt recip estimation
2020-04-01 16:23:43 +08:00
PowerPC
[PowerPC] Remove unnecessary XSRSP instruction
2020-04-03 11:05:14 +08:00
RISCV
[LegalizeTypes][RISCV] Correctly sign-extend comparison for ATOMIC_CMP_XCHG
2020-04-01 15:51:26 +01:00
SPARC
[Sparc] Fix incorrect operand for matching CMPri pattern
2020-03-02 11:36:32 +08:00
SystemZ
[LoopDataPrefetch + SystemZ] Let target decide on prefetching for each loop.
2020-04-02 14:57:46 +02:00
Thumb
[DAGCombine] Skip PostInc combine with later users
2020-03-23 08:39:53 +00:00
Thumb2
[ARM] MVE VMULL patterns
2020-04-02 10:57:40 +01:00
VE
[VE] Target-specific bit size for sjljehprepare
2020-03-10 17:51:16 +01:00
WebAssembly
[WebAssembly] EmscriptenEHSjLj: Mark __invoke_ functions as imported
2020-04-01 16:33:33 -07:00
WinCFGuard
…
WinEH
…
X86
[X86] Add Indirect Thunk Support to X86 to mitigate Load Value Injection (LVI)
2020-04-03 00:34:39 -07:00
XCore
[XCore] Add instruction pattern for bitrev
2020-02-21 09:28:49 +08:00