b794baf8e7
This commit introduces the VectorInstrContext (VIC) infrastructure to improve cost estimates for insert/extracts based on the context instruction in which the insert/extract is used. This is similar to CastContextHint, and allows providing context on how the insert/extract is going to be used before creating IR. This is useful in the LoopVectorizer, where costs need to estimated before creating IR. The new hint currently only replaces an existing check in AArch64, but new uses will be introduced in follow-ups, including https://github.com/llvm/llvm-project/pull/177201. PR: https://github.com/llvm/llvm-project/pull/175982
75 lines
3.2 KiB
C++
75 lines
3.2 KiB
C++
//===- R600TargetTransformInfo.h - R600 specific TTI --------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// This file a TargetTransformInfoImplBase conforming object specific to the
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/// R600 target machine. It uses the target's detailed information to
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/// provide more precise answers to certain TTI queries, while letting the
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/// target independent and default TTI implementations handle the rest.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_AMDGPU_R600TARGETTRANSFORMINFO_H
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#define LLVM_LIB_TARGET_AMDGPU_R600TARGETTRANSFORMINFO_H
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#include "AMDGPUTargetTransformInfo.h"
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#include "llvm/CodeGen/BasicTTIImpl.h"
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namespace llvm {
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class R600Subtarget;
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class AMDGPUTargetLowering;
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class R600TTIImpl final : public BasicTTIImplBase<R600TTIImpl> {
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using BaseT = BasicTTIImplBase<R600TTIImpl>;
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using TTI = TargetTransformInfo;
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friend BaseT;
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const R600Subtarget *ST;
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const AMDGPUTargetLowering *TLI;
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AMDGPUTTIImpl CommonTTI;
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public:
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explicit R600TTIImpl(const AMDGPUTargetMachine *TM, const Function &F);
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const R600Subtarget *getST() const { return ST; }
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const AMDGPUTargetLowering *getTLI() const { return TLI; }
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void getUnrollingPreferences(Loop *L, ScalarEvolution &SE,
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TTI::UnrollingPreferences &UP,
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OptimizationRemarkEmitter *ORE) const override;
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void getPeelingPreferences(Loop *L, ScalarEvolution &SE,
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TTI::PeelingPreferences &PP) const override;
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unsigned getHardwareNumberOfRegisters(bool Vec) const;
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unsigned getNumberOfRegisters(unsigned ClassID) const override;
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TypeSize
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getRegisterBitWidth(TargetTransformInfo::RegisterKind Vector) const override;
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unsigned getMinVectorRegisterBitWidth() const override;
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unsigned getLoadStoreVecRegBitWidth(unsigned AddrSpace) const override;
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bool isLegalToVectorizeMemChain(unsigned ChainSizeInBytes, Align Alignment,
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unsigned AddrSpace) const;
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bool isLegalToVectorizeLoadChain(unsigned ChainSizeInBytes, Align Alignment,
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unsigned AddrSpace) const override;
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bool isLegalToVectorizeStoreChain(unsigned ChainSizeInBytes, Align Alignment,
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unsigned AddrSpace) const override;
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unsigned getMaxInterleaveFactor(ElementCount VF) const override;
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InstructionCost getCFInstrCost(unsigned Opcode, TTI::TargetCostKind CostKind,
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const Instruction *I = nullptr) const override;
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using BaseT::getVectorInstrCost;
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InstructionCost
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getVectorInstrCost(unsigned Opcode, Type *ValTy, TTI::TargetCostKind CostKind,
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unsigned Index, const Value *Op0, const Value *Op1,
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TTI::VectorInstrContext VIC =
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TTI::VectorInstrContext::None) const override;
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};
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} // end namespace llvm
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#endif // LLVM_LIB_TARGET_AMDGPU_R600TARGETTRANSFORMINFO_H
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