11ab23c33d
Both conceptually belong to the same subtarget, so it should not be necessary to pass in the context TargetRegisterInfo to any TargetInstrInfo member. Add this reference so those superfluous arguments can be removed. Most targets placed their TargetRegisterInfo as a member in TargetInstrInfo. A few had this owned by the TargetSubtargetInfo, so unify all targets to look the same.
47 lines
1.5 KiB
C++
47 lines
1.5 KiB
C++
//===-- ARMInstrInfo.h - ARM Instruction Information ------------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the ARM implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_ARM_ARMINSTRINFO_H
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#define LLVM_LIB_TARGET_ARM_ARMINSTRINFO_H
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#include "ARMBaseInstrInfo.h"
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#include "ARMRegisterInfo.h"
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namespace llvm {
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class ARMSubtarget;
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class ARMInstrInfo : public ARMBaseInstrInfo {
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ARMRegisterInfo RI;
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public:
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explicit ARMInstrInfo(const ARMSubtarget &STI);
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/// Return the noop instruction to use for a noop.
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MCInst getNop() const override;
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// Return the non-pre/post incrementing version of 'Opc'. Return 0
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// if there is not such an opcode.
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unsigned getUnindexedOpcode(unsigned Opc) const override;
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/// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
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/// such, whenever a client has an instance of instruction info, it should
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/// always be able to get register info as well (through this method).
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///
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const ARMRegisterInfo &getRegisterInfo() const { return RI; }
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private:
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void expandLoadStackGuard(MachineBasicBlock::iterator MI) const override;
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};
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}
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#endif
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