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llvm-project/llvm/lib/Target/RISCV
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Kavin Gnanapandithan 33a14cbe35
[RISCV] Add guard to prevent GPRPair merge on targets without Zdinx or P (#186600) 
Resolves #186527.

The issue points out that GPRPair merge logic in the RISCVMoveMerger
pass was being called on a target without `zdinx` or `experimental-P`,
triggering an unreachable in `getGPRPairCopyOpcode`.

This patch fixes this issue by guarding `isEvenRegisterCopy` and
`isOddRegisterCopy` to return false when neither Zdinx nor P is present.
2026-03-22 10:26:33 -07:00
..
AsmParser
[RISCV] Add register group overlap checks to the assembler for vector indexed segment load (#184963)
2026-03-12 14:22:30 +08:00
Disassembler
[RISCV] Use decodeVMaskReg for VMaskCarryInOp. NFC (#177742)
2026-01-25 00:41:16 +00:00
GISel
[RISCV][GISel] Replace buildInstr with BuildMI (#183714)
2026-03-04 11:21:27 +08:00
MCA
[RISCV] Rename nf->nfields in MC layer. NFC (#179365)
2026-02-02 22:29:24 -08:00
MCTargetDesc
[RISCV] Relax out of range Zibi conditional branches (#186965)
2026-03-19 21:07:53 +08:00
TargetInfo
…
CMakeLists.txt
[RISCV][NFC] Add RISCVVSETVLIInfoAnalysis
2026-01-12 12:00:55 +08:00
RISCV.h
[llvm][RISCV] Implement Zilsd load/store pair optimization (#158640)
2025-11-21 05:04:05 +00:00
RISCV.td
[RISCV] Add SpacemiT X100 base scheduling model (#178189)
2026-02-09 11:36:45 +08:00
RISCVAsmPrinter.cpp
[RISCV] Relax codegen predicates for HINT-based instructions (#179872)
2026-03-02 17:24:22 +08:00
RISCVCallingConv.cpp
[RISCV][llvm] Handle calling convention for P extension fixed vectors (#176093)
2026-01-19 12:09:27 +08:00
RISCVCallingConv.h
…
RISCVCallingConv.td
…
RISCVCodeGenPrepare.cpp
[RISCV] Remove last use of @llvm.experimental.vp.splat in RISCVCodeGenPrepare. NFCI (#170543)
2025-12-08 06:09:03 +00:00
RISCVCombine.td
[RISCV][GISel] Fold G_FCONSTANT 0.0 store into G_CONSTANT x0 (#163008)
2025-10-23 15:50:04 +08:00
RISCVConstantPoolValue.cpp
…
RISCVConstantPoolValue.h
[Target] Add "override" where appropriate (NFC) (#165083)
2025-10-25 06:23:43 -07:00
RISCVDeadRegisterDefinitions.cpp
CodeGen: Remove TRI argument from getRegClass (#158225)
2025-11-10 15:43:55 -08:00
RISCVExpandAtomicPseudoInsts.cpp
[RISCV] 'Zalrsc' may permit non-base instructions (#165042)
2025-10-28 12:51:11 -07:00
RISCVExpandPseudoInsts.cpp
[RISCV] SFB with Immediates to QC.MVccI (#186555)
2026-03-19 09:51:38 -07:00
RISCVFeatures.td
[RISCV] Add codegen patterns to support short forward branches with immediates (#185643)
2026-03-13 16:55:39 -07:00
RISCVFoldMemOffset.cpp
[RISCV] Add Zilsd to RISCVFoldMemOffset (#176544)
2026-01-19 11:19:30 +05:30
RISCVFrameLowering.cpp
[llvm][RISCV] Use zilsd for callee-saved register spill/restore on RV32 (#184794)
2026-03-10 03:17:35 +00:00
RISCVFrameLowering.h
[CodeGen] Replace (Min,Max)CSFrameIndex with flag on frame object [NFCI] (#170905)
2025-12-06 14:00:55 -08:00
RISCVGatherScatterLowering.cpp
[IR] Replace alignment argument with attribute on masked intrinsics (#163802)
2025-10-20 08:50:09 +00:00
RISCVGISel.td
[RISCV][NFC] Simplify Imm range checks (#170497)
2025-12-04 06:04:49 +01:00
RISCVIndirectBranchTracking.cpp
[RISCV] Emit lpad for function with returns-twice attribute (#170520)
2025-12-04 13:25:57 +08:00
RISCVInsertReadWriteCSR.cpp
…
RISCVInsertVSETVLI.cpp
[RISCV] Add RISCVII::getTWidenOpNum. NFC (#182335)
2026-02-19 22:11:27 -08:00
RISCVInsertWriteVXRM.cpp
[llvm] Use "= default" (NFC) (#166088)
2025-11-02 17:16:47 -08:00
RISCVInstrFormats.td
[RISCV] Make ElementsDependOn opt-in instead of opt-out. NFCI (#181601)
2026-02-26 01:07:25 +08:00
RISCVInstrFormatsC.td
[RISCV] Add OPC_C0/C1/C2 named values to tablegen. NFC (#178325)
2026-01-27 22:55:47 -08:00
RISCVInstrFormatsSpacemitV.td
[RISCV] Add contraints for SpacemiT X60 AI VDot Insts (#174364)
2026-03-06 10:23:53 +08:00
RISCVInstrFormatsV.td
[RISCV] Rename RVVConstraint->VS1VS2Constraint. NFC (#182688)
2026-02-23 08:58:14 -08:00
RISCVInstrFormatsXAIF.td
[RISCV] AI Foundry ET extensions for RISC-V (#174571)
2026-01-13 12:54:11 -08:00
RISCVInstrGISel.td
[GISel] Add G_CTLS Opcode and combines, lower to cls(w) (#175069)
2026-01-16 13:22:18 -08:00
RISCVInstrInfo.cpp
[RISCV] Use RISCVCC::getInverseBranchOpcode in RISCVInstrInfo::reverseBranchCondition. NFC (#185752)
2026-03-10 14:20:43 -07:00
RISCVInstrInfo.h
[RISCV] Sink instructions so AVL dominates in RISCVVLOptimizer (#184155)
2026-03-04 05:46:26 +00:00
RISCVInstrInfo.td
[RISCV] Relax out of range Zibi conditional branches (#186965)
2026-03-19 21:07:53 +08:00
RISCVInstrInfoA.td
[RISCV] Use GPR instead of ixlenimm for sextshamt in PseudoMaskedAMOMinMax. NFC (#171736)
2025-12-10 20:43:46 -08:00
RISCVInstrInfoC.td
[RISCV] Deprecate RISCVSubtarget::hasStdExtCOrZcd() and hasStdExtCOrZcfOrZce(). (#179762)
2026-02-04 13:00:21 -08:00
RISCVInstrInfoD.td
[RISCV] Fix fcanonicalize for Z*inx (#175984)
2026-01-15 23:03:38 -08:00
RISCVInstrInfoF.td
[RISCV] Document some of the names we require for getNamedOperandIdx. NFC (#182687)
2026-02-24 10:51:54 -08:00
RISCVInstrInfoM.td
…
RISCVInstrInfoP.td
[RISCV] Fold waddau/wsubau to waddu/wsubu when possible (#186635)
2026-03-16 09:02:37 -07:00
RISCVInstrInfoQ.td
…
RISCVInstrInfoSFB.td
[RISCV] Add codegen patterns to support short forward branches with immediates (#185643)
2026-03-13 16:55:39 -07:00
RISCVInstrInfoV.td
[RISCV] Add register overlap checks to the assembler for vector indexed segment load (#184569)
2026-03-05 20:06:50 -08:00
RISCVInstrInfoVPseudos.td
[RISCV] Document some of the names we require for getNamedOperandIdx. NFC (#182687)
2026-02-24 10:51:54 -08:00
RISCVInstrInfoVSDPatterns.td
[RISCV] Add ComplexPatterns for matching xor/vmnot_vl+vmset_vl. NFC (#182071)
2026-02-19 16:41:48 +00:00
RISCVInstrInfoVVLPatterns.td
[RISCV] Add ComplexPatterns for matching xor/vmnot_vl+vmset_vl. NFC (#182071)
2026-02-19 16:41:48 +00:00
RISCVInstrInfoXAIF.td
[RISCV] AI Foundry ET extensions for RISC-V (#174571)
2026-01-13 12:54:11 -08:00
RISCVInstrInfoXAndes.td
[RISCV] Remove unnecessary mayRaiseFPException from NDS_VFWCVT_S_BF16
2026-03-13 15:05:20 +08:00
RISCVInstrInfoXCV.td
[RISCV][NFC] Push riscv_selectcc PatFrag Inwards (#175902)
2026-01-14 10:22:47 -08:00
RISCVInstrInfoXMips.td
[RISC-V] Reduce code duplication for uimm*_lsb* operands. NFC
2026-01-25 21:45:00 -08:00
RISCVInstrInfoXqccmp.td
[RISCV] Add OPC_C0/C1/C2 named values to tablegen. NFC (#178325)
2026-01-27 22:55:47 -08:00
RISCVInstrInfoXqci.td
[RISCV] Relax out of range Zibi conditional branches (#186965)
2026-03-19 21:07:53 +08:00
RISCVInstrInfoXRivos.td
[TabelGen] Use ID{n-m} for outer let statements (#187436)
2026-03-19 18:38:43 +08:00
RISCVInstrInfoXSf.td
[RISCV] Make ElementsDependOn opt-in instead of opt-out. NFCI (#181601)
2026-02-26 01:07:25 +08:00
RISCVInstrInfoXSfmm.td
[RISCV] Document some of the names we require for getNamedOperandIdx. NFC (#182687)
2026-02-24 10:51:54 -08:00
RISCVInstrInfoXSpacemiT.td
[RISCV] Add contraints for SpacemiT X60 AI VDot Insts (#174364)
2026-03-06 10:23:53 +08:00
RISCVInstrInfoXTHead.td
[RISCV] Rename add_like pattern -> riscv_add_like (#187306)
2026-03-18 16:26:03 +00:00
RISCVInstrInfoXVentana.td
…
RISCVInstrInfoXwch.td
[RISCV] Add OPC_C0/C1/C2 named values to tablegen. NFC (#178325)
2026-01-27 22:55:47 -08:00
RISCVInstrInfoZa.td
[RISCV] Reorder ins/outs of atomic instruction to match their assembly order. NFC (#162411)
2025-10-07 22:24:52 -07:00
RISCVInstrInfoZalasr.td
[RISCV][GISel] Add manual isel for s8/s16/s32 load/store for the GPR bank. (#161995)
2025-10-07 21:30:09 -07:00
RISCVInstrInfoZb.td
[RISCV] Rename add_like pattern -> riscv_add_like (#187306)
2026-03-18 16:26:03 +00:00
RISCVInstrInfoZc.td
[RISCV] Add OPC_C0/C1/C2 named values to tablegen. NFC (#178325)
2026-01-27 22:55:47 -08:00
RISCVInstrInfoZclsd.td
…
RISCVInstrInfoZcmop.td
[RISCV] Make MOP/HINT-based instruction mnemonics always available (#178609)
2026-02-03 23:39:53 +08:00
RISCVInstrInfoZfa.td
[RISCV] Remove decodeRTZArg. NFC (#177744)
2026-01-24 11:08:57 -08:00
RISCVInstrInfoZfbfmin.td
[RISCV][NFC] Push riscv_selectcc PatFrag Inwards (#175902)
2026-01-14 10:22:47 -08:00
RISCVInstrInfoZfh.td
[RISCV] Fix fcanonicalize for Z*inx (#175984)
2026-01-15 23:03:38 -08:00
RISCVInstrInfoZibi.td
[RISCV] Relax out of range Zibi conditional branches (#186965)
2026-03-19 21:07:53 +08:00
RISCVInstrInfoZicbo.td
…
RISCVInstrInfoZicfiss.td
[RISCV] Make MOP/HINT-based instruction mnemonics always available (#178609)
2026-02-03 23:39:53 +08:00
RISCVInstrInfoZicond.td
…
RISCVInstrInfoZilsd.td
[llvm][RISCV] Implement Zilsd load/store pair optimization (#158640)
2025-11-21 05:04:05 +00:00
RISCVInstrInfoZimop.td
…
RISCVInstrInfoZk.td
…
RISCVInstrInfoZvabd.td
[RISCV] Make ElementsDependOn opt-in instead of opt-out. NFCI (#181601)
2026-02-26 01:07:25 +08:00
RISCVInstrInfoZvdot4a8i.td
[RISCV][llvm] Use [u]int32 vector for input arguments for zvdot4a8i (#184089)
2026-03-09 14:06:00 +08:00
RISCVInstrInfoZvfbf.td
[RISCV] Make ElementsDependOn opt-in instead of opt-out. NFCI (#181601)
2026-02-26 01:07:25 +08:00
RISCVInstrInfoZvfofp8min.td
[RISCV] Convert some multiclasses in RISCVInstrInfoV.td to classes if they only have one child def. NFC (#181408)
2026-02-13 20:31:49 -08:00
RISCVInstrInfoZvk.td
[RISCV] Make zvknha a subset of zvknhb (#178680)
2026-03-10 08:40:49 +00:00
RISCVInstrInfoZvzip.td
[RISCV][MC] Add support of Zvzip extension (#185614)
2026-03-11 14:22:02 +08:00
RISCVInstrPredicates.td
[RISCV] Fix IDiv/IRem scheduling data for RV32 cores that use the SiFive7 model (#187331)
2026-03-18 13:08:18 -07:00
RISCVInterleavedAccess.cpp
[RISCV]Lower one active interleaved load to normal segmented load (#185602)
2026-03-11 18:08:32 +08:00
RISCVISelDAGToDAG.cpp
[RISCV] Select (sext_inreg (sra X, C), i8/i16) as slli+srai. (#186956)
2026-03-17 08:01:40 -07:00
RISCVISelDAGToDAG.h
[RISCV] Make selectShiftMask32/selectShiftMask64 a template function. NFC (#185957)
2026-03-11 14:10:59 -07:00
RISCVISelLowering.cpp
[RISCV][NFC] Remove duplicate setTargetDAGCombine registrations (#186928)
2026-03-17 13:09:22 +08:00
RISCVISelLowering.h
[LLVM][TTI] Remove the isVScaleKnownToBeAPowerOfTwo hook. (#183292)
2026-02-25 14:09:52 +00:00
RISCVLandingPadSetup.cpp
…
RISCVLateBranchOpt.cpp
…
RISCVLoadStoreOptimizer.cpp
[NFC][MI] Tidy Up RegState enum use (2/2) (#177090)
2026-01-23 00:19:03 -08:00
RISCVMachineFunctionInfo.cpp
…
RISCVMachineFunctionInfo.h
[RISCV] improve musttail support (#170547)
2026-02-11 17:27:51 +01:00
RISCVMachineScheduler.cpp
[RISCV] Schedule RVV instructions with compatible vtype/vl first
2026-01-12 12:02:39 +08:00
RISCVMachineScheduler.h
[RISCV] Schedule RVV instructions with compatible vtype/vl first
2026-01-12 12:02:39 +08:00
RISCVMacroFusion.td
[NFC] Move fusion- to start of Fusion Feature Name (#185146)
2026-03-06 21:57:48 -08:00
RISCVMakeCompressible.cpp
[RISCV] Deprecate RISCVSubtarget::hasStdExtCOrZcd() and hasStdExtCOrZcfOrZce(). (#179762)
2026-02-04 13:00:21 -08:00
RISCVMergeBaseOffset.cpp
[RISCV] Fold shladd into Xqcisls scaled load/store in RISCVMergeBaseOffset (#182221)
2026-02-21 15:36:36 +05:30
RISCVMoveMerger.cpp
[RISCV] Add guard to prevent GPRPair merge on targets without Zdinx or P (#186600)
2026-03-22 10:26:33 -07:00
RISCVOptWInstrs.cpp
[RISCV][NFC] Prepare for Short Forward Branch of branches with immediates (#182456)
2026-03-03 12:38:00 +05:30
RISCVPassRegistry.def
[RISCV][NewPM] Port RISCVCodeGenPrepare to the new pass manager (#168381)
2025-11-19 06:51:18 +00:00
RISCVPfmCounters.td
…
RISCVPostRAExpandPseudoInsts.cpp
[RISCV] Add basic scalar support for MERGE, MVM, and MVMN from P extension (#180677)
2026-02-10 13:39:34 -08:00
RISCVProcessors.td
[RISCV] Add scheduling models for sifive-x160 and sifive-x180 (#187089)
2026-03-19 10:17:42 -07:00
RISCVProfiles.td
…
RISCVPromoteConstant.cpp
[RISCV] Introduce pass to promote double constants to a global array (#160536)
2025-11-05 14:31:17 +00:00
RISCVPushPopOptimizer.cpp
…
RISCVRedundantCopyElimination.cpp
[RISCV] Add support for Zibi experimental extension in RISCVRedundantCopyElimination (#174920)
2026-01-09 14:00:53 +08:00
RISCVRegisterInfo.cpp
[RISCV] Treat zext.h as a separate instruction from pack(w) with Zbkb. (#183364)
2026-02-25 20:46:37 -08:00
RISCVRegisterInfo.h
[RegAlloc] Change the computation of CSRCost (#177226)
2026-02-04 10:08:57 -08:00
RISCVRegisterInfo.td
[RISCV] Add a template function for disassembling LMUL=2/4/8 vector registers. NFC (#177681)
2026-01-23 15:58:55 -08:00
RISCVSchedAndes45.td
[RISCV] Update Andes45 vector permutation scheduling info (#185591)
2026-03-12 09:49:18 +08:00
RISCVSchedGenericOOO.td
…
RISCVSchedMIPSP8700.td
…
RISCVSchedRocket.td
…
RISCVSchedSiFive7.td
[RISCV] Fix the pipe used by fmv.x.<fp>/<fp>.x in SiFive7 sched model (#187740)
2026-03-20 12:21:35 -07:00
RISCVSchedSiFiveP400.td
…
RISCVSchedSiFiveP500.td
…
RISCVSchedSiFiveP600.td
[RISCV] Fix wrong use of SiFiveP400GetVLMAX in RISCVSchedSiFiveP600 (#171562)
2025-12-10 13:59:13 +08:00
RISCVSchedSiFiveP800.td
…
RISCVSchedSpacemitX60.td
[RISCV] Assign separate latencies for vector COPYs in SpacemitX60 scheduling model (#172556)
2025-12-18 07:04:42 -08:00
RISCVSchedSpacemitX100.td
[RISCV] Add SpacemiT X100 base scheduling model (#178189)
2026-02-09 11:36:45 +08:00
RISCVSchedSyntacoreSCR1.td
…
RISCVSchedSyntacoreSCR7.td
…
RISCVSchedSyntacoreSCR345.td
…
RISCVSchedTTAscalonX.td
[RISCV] Rename Tenstorrent Ascalon D8 to Ascalon X (#178199)
2026-01-27 21:31:51 +00:00
RISCVSchedule.td
[RISCV] Assign separate latencies for vector COPYs in SpacemitX60 scheduling model (#172556)
2025-12-18 07:04:42 -08:00
RISCVScheduleV.td
[RISCV] LMUL lists for indexed and strided loads (#169756)
2025-12-05 13:10:22 -08:00
RISCVScheduleXSf.td
[RISCV] Add LLVM IR intrinsics and codegen for XSfvfexp* and XSfvfexpa* (#164499)
2025-10-24 18:09:03 +00:00
RISCVScheduleZb.td
…
RISCVScheduleZvk.td
…
RISCVSchedXiangShanNanHu.td
…
RISCVSelectionDAGInfo.cpp
[RISCV][llvm] Rename zvqdotq to zvdot4a8i (#179393)
2026-02-24 04:44:07 +00:00
RISCVSelectionDAGInfo.h
…
RISCVSubtarget.cpp
[RISCV] Remove -riscv-enable-p-ext-simd-codegen (#183156)
2026-02-25 08:43:55 -08:00
RISCVSubtarget.h
[RISCV] Support scalar bitreverse using P extension rev instruction. (#183245)
2026-02-25 12:42:59 -08:00
RISCVSystemOperands.td
[RISCV] AI Foundry ET extensions for RISC-V (#174571)
2026-01-13 12:54:11 -08:00
RISCVTargetMachine.cpp
[CodGen] Port UnpackMachineBundles to new pass manager (#184918)
2026-03-17 09:01:37 -07:00
RISCVTargetMachine.h
…
RISCVTargetObjectFile.cpp
[RISCV] Put Large Code Model Constant Pools in .text (#151393)
2026-03-02 13:17:06 -08:00
RISCVTargetObjectFile.h
[RISCV] Put Large Code Model Constant Pools in .text (#151393)
2026-03-02 13:17:06 -08:00
RISCVTargetTransformInfo.cpp
[CodeGen] Drop uses of BranchInst (#186391)
2026-03-13 21:51:38 +00:00
RISCVTargetTransformInfo.h
[RISCV] Disable use of scalable vectors for VLEN=32 (#185553)
2026-03-11 15:11:50 +08:00
RISCVVectorMaskDAGMutation.cpp
…
RISCVVectorPeephole.cpp
[RISCV] Remove RISCVVectorPeephole::tryToReduceVL (#184297)
2026-03-05 03:58:45 +00:00
RISCVVLOptimizer.cpp
[CodeGen] Declare MachineCycleInfo in headers (#187494)
2026-03-19 13:32:59 +00:00
RISCVVMV0Elimination.cpp
…
RISCVVSETVLIInfoAnalysis.cpp
[RISCV] Add RISCVII::getTWidenOpNum. NFC (#182335)
2026-02-19 22:11:27 -08:00
RISCVVSETVLIInfoAnalysis.h
[RISCV][NFC] Add RISCVVSETVLIInfoAnalysis
2026-01-12 12:00:55 +08:00
RISCVZacasABIFix.cpp
…
RISCVZilsdOptimizer.cpp
[llvm][RISCV] Make X0 register pair legal in pre-ra pass (#169164)
2026-01-21 14:13:44 +08:00