ade43a54d4
Initial support for acquire-release atomics, specified as part of https://github.com/WebAssembly/shared-everything-threads This adds an ordering operand to atomic loads, stores, RMWs, wait/notify, and fences. It currently defaults to 0 and ISel is not updated yet, so atomics produced by the compiler will still always be seqcst. Asm parsing and printing, binary emission and disassembly are all updated. Binary emission will always use the old encoding because the encoding is smaller, and to get backwards compatibility for free.
267 lines
10 KiB
C++
267 lines
10 KiB
C++
//=- WebAssemblyMCCodeEmitter.cpp - Convert WebAssembly code to machine code -//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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///
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/// \file
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/// This file implements the WebAssemblyMCCodeEmitter class.
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///
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//===----------------------------------------------------------------------===//
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#include "MCTargetDesc/WebAssemblyFixupKinds.h"
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#include "MCTargetDesc/WebAssemblyMCTargetDesc.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/MC/MCCodeEmitter.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCFixup.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCInstrInfo.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/MC/MCSymbol.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/EndianStream.h"
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#include "llvm/Support/LEB128.h"
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#include "llvm/Support/SMLoc.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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#define DEBUG_TYPE "mccodeemitter"
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STATISTIC(MCNumEmitted, "Number of MC instructions emitted.");
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STATISTIC(MCNumFixups, "Number of MC fixups created.");
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namespace {
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class WebAssemblyMCCodeEmitter final : public MCCodeEmitter {
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const MCInstrInfo &MCII;
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MCContext &Ctx;
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// Implementation generated by tablegen.
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uint64_t getBinaryCodeForInstr(const MCInst &MI,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const;
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void encodeInstruction(const MCInst &MI, SmallVectorImpl<char> &CB,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const override;
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void encodeP2AlignAndMemOrder(const MCInst &MI, unsigned P2AlignIdx,
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const MCInstrDesc &Desc,
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const MCSubtargetInfo &STI, raw_ostream &OS,
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SmallVectorImpl<MCFixup> &Fixups,
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uint64_t Start) const;
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uint8_t getEncodedMemOrder(uint8_t Order, unsigned Opcode) const;
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public:
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WebAssemblyMCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx)
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: MCII(MCII), Ctx{Ctx} {}
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};
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} // end anonymous namespace
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MCCodeEmitter *llvm::createWebAssemblyMCCodeEmitter(const MCInstrInfo &MCII,
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MCContext &Ctx) {
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return new WebAssemblyMCCodeEmitter(MCII, Ctx);
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}
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uint8_t WebAssemblyMCCodeEmitter::getEncodedMemOrder(uint8_t Order,
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unsigned Opcode) const {
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if (Order == wasm::WASM_MEM_ORDER_ACQ_REL) {
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StringRef Name = MCII.getName(Opcode);
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if (Name.contains("RMW") || Name.contains("CMPXCHG"))
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return wasm::WASM_MEM_ORDER_RMW_ACQ_REL;
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}
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return Order;
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}
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void WebAssemblyMCCodeEmitter::encodeP2AlignAndMemOrder(
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const MCInst &MI, unsigned P2AlignIdx, const MCInstrDesc &Desc,
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const MCSubtargetInfo &STI, raw_ostream &OS,
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SmallVectorImpl<MCFixup> &Fixups, uint64_t Start) const {
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uint64_t P2Align = MI.getOperand(P2AlignIdx).getImm();
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uint8_t Order = wasm::WASM_MEM_ORDER_SEQ_CST;
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// Atomic instructions always have an ordering, but if it's SEQ_CST then we
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// don't use the relaxed-atomics encoding (even if relaxed-atomics is
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// enabled) because the original encoding is smaller.
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if (P2AlignIdx > 0 && Desc.operands()[P2AlignIdx - 1].OperandType ==
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WebAssembly::OPERAND_MEMORDER) {
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Order = MI.getOperand(P2AlignIdx - 1).getImm();
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if (Order != wasm::WASM_MEM_ORDER_SEQ_CST) {
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assert(STI.getFeatureBits()[WebAssembly::FeatureRelaxedAtomics] &&
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"Non-default atomic ordering but feature not enabled");
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P2Align |= wasm::WASM_MEMARG_HAS_MEM_ORDER;
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}
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}
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encodeULEB128(P2Align, OS);
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// Memory index will go here once we support multi-memory.
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if (P2Align & wasm::WASM_MEMARG_HAS_MEM_ORDER) {
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support::endian::write<uint8_t>(OS,
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getEncodedMemOrder(Order, MI.getOpcode()),
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llvm::endianness::little);
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}
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}
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void WebAssemblyMCCodeEmitter::encodeInstruction(
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const MCInst &MI, SmallVectorImpl<char> &CB,
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SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const {
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raw_svector_ostream OS(CB);
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uint64_t Start = OS.tell();
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uint64_t Binary = getBinaryCodeForInstr(MI, Fixups, STI);
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if (Binary < (1 << 8)) {
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OS << uint8_t(Binary);
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} else if (Binary < (1 << 16)) {
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OS << uint8_t(Binary >> 8);
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encodeULEB128(uint8_t(Binary), OS);
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} else if (Binary < (1 << 24)) {
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OS << uint8_t(Binary >> 16);
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encodeULEB128(uint16_t(Binary), OS);
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} else {
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llvm_unreachable("Very large (prefix + 3 byte) opcodes not supported");
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}
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// For br_table instructions, encode the size of the table. In the MCInst,
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// there's an index operand (if not a stack instruction), one operand for
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// each table entry, and the default operand.
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unsigned Opcode = MI.getOpcode();
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if (Opcode == WebAssembly::BR_TABLE_I32_S ||
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Opcode == WebAssembly::BR_TABLE_I64_S)
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encodeULEB128(MI.getNumOperands() - 1, OS);
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if (Opcode == WebAssembly::BR_TABLE_I32 ||
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Opcode == WebAssembly::BR_TABLE_I64)
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encodeULEB128(MI.getNumOperands() - 2, OS);
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const MCInstrDesc &Desc = MCII.get(Opcode);
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for (unsigned I = 0, E = MI.getNumOperands(); I < E; ++I) {
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const MCOperand &MO = MI.getOperand(I);
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if (MO.isReg()) {
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/* nothing to encode */
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} else if (MO.isImm()) {
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if (I < Desc.getNumOperands()) {
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const MCOperandInfo &Info = Desc.operands()[I];
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LLVM_DEBUG(dbgs() << "Encoding immediate: type="
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<< int(Info.OperandType) << "\n");
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switch (Info.OperandType) {
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case WebAssembly::OPERAND_I32IMM:
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encodeSLEB128(int32_t(MO.getImm()), OS);
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break;
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case WebAssembly::OPERAND_P2ALIGN:
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encodeP2AlignAndMemOrder(MI, I, Desc, STI, OS, Fixups, Start);
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break;
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case WebAssembly::OPERAND_OFFSET32:
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encodeULEB128(uint32_t(MO.getImm()), OS);
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break;
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case WebAssembly::OPERAND_I64IMM:
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encodeSLEB128(MO.getImm(), OS);
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break;
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case WebAssembly::OPERAND_SIGNATURE:
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case WebAssembly::OPERAND_VEC_I8IMM:
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support::endian::write<uint8_t>(OS, MO.getImm(),
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llvm::endianness::little);
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break;
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case WebAssembly::OPERAND_MEMORDER: {
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// If there is a p2align operand (everything but fence) it is encoded
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// together with the mem ordering (in the next iteration).
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if (I + 1 < Desc.getNumOperands() &&
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Desc.operands()[I + 1].OperandType ==
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WebAssembly::OPERAND_P2ALIGN)
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break;
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uint8_t Val = getEncodedMemOrder(MO.getImm(), Opcode);
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if (STI.getFeatureBits()[WebAssembly::FeatureRelaxedAtomics]) {
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support::endian::write<uint8_t>(OS, Val, llvm::endianness::little);
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} else {
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assert(Opcode == WebAssembly::ATOMIC_FENCE_S);
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support::endian::write<uint8_t>(OS, 0, llvm::endianness::little);
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}
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break;
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}
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case WebAssembly::OPERAND_VEC_I16IMM:
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support::endian::write<uint16_t>(OS, MO.getImm(),
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llvm::endianness::little);
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break;
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case WebAssembly::OPERAND_VEC_I32IMM:
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support::endian::write<uint32_t>(OS, MO.getImm(),
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llvm::endianness::little);
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break;
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case WebAssembly::OPERAND_VEC_I64IMM:
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support::endian::write<uint64_t>(OS, MO.getImm(),
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llvm::endianness::little);
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break;
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case WebAssembly::OPERAND_GLOBAL:
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Ctx.reportError(
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SMLoc(),
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Twine("Wasm globals should only be accessed symbolically!"));
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break;
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default:
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encodeULEB128(uint64_t(MO.getImm()), OS);
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}
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} else {
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// Variadic immediate operands are br_table's destination operands or
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// try_table's operands (# of catch clauses, catch sub-opcodes, or catch
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// clause destinations)
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assert(WebAssembly::isBrTable(Opcode) ||
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Opcode == WebAssembly::TRY_TABLE_S);
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encodeULEB128(uint32_t(MO.getImm()), OS);
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}
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} else if (MO.isSFPImm()) {
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uint32_t F = MO.getSFPImm();
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support::endian::write<uint32_t>(OS, F, llvm::endianness::little);
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} else if (MO.isDFPImm()) {
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uint64_t D = MO.getDFPImm();
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support::endian::write<uint64_t>(OS, D, llvm::endianness::little);
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} else if (MO.isExpr()) {
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llvm::MCFixupKind FixupKind;
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size_t PaddedSize = 5;
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if (I < Desc.getNumOperands()) {
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const MCOperandInfo &Info = Desc.operands()[I];
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switch (Info.OperandType) {
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case WebAssembly::OPERAND_I32IMM:
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FixupKind = WebAssembly::fixup_sleb128_i32;
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break;
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case WebAssembly::OPERAND_I64IMM:
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FixupKind = WebAssembly::fixup_sleb128_i64;
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PaddedSize = 10;
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break;
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case WebAssembly::OPERAND_FUNCTION32:
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case WebAssembly::OPERAND_TABLE:
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case WebAssembly::OPERAND_OFFSET32:
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case WebAssembly::OPERAND_SIGNATURE:
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case WebAssembly::OPERAND_TYPEINDEX:
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case WebAssembly::OPERAND_GLOBAL:
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case WebAssembly::OPERAND_TAG:
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FixupKind = WebAssembly::fixup_uleb128_i32;
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break;
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case WebAssembly::OPERAND_OFFSET64:
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FixupKind = WebAssembly::fixup_uleb128_i64;
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PaddedSize = 10;
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break;
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default:
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llvm_unreachable("unexpected symbolic operand kind");
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}
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} else {
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// Variadic expr operands are try_table's catch/catch_ref clauses' tags.
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assert(Opcode == WebAssembly::TRY_TABLE_S);
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FixupKind = WebAssembly::fixup_uleb128_i32;
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}
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Fixups.push_back(
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MCFixup::create(OS.tell() - Start, MO.getExpr(), FixupKind));
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++MCNumFixups;
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encodeULEB128(0, OS, PaddedSize);
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} else {
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llvm_unreachable("unexpected operand kind");
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}
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}
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++MCNumEmitted; // Keep track of the # of mi's emitted.
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}
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#include "WebAssemblyGenMCCodeEmitter.inc"
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