b4b8d4e5d0
We need to check that OpX does not write the sources of OpY, but if we swap OpX and OpY with respect to program order, the check was not swapped correctly. The checks on gfx1250 can be relaxed slightly, that is planned for a future patch. --------- Co-authored-by: Matt Arsenault <arsenm2@gmail.com>
109 lines
5.0 KiB
LLVM
109 lines
5.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 %s -o - | FileCheck -check-prefix=GFX9 %s
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1030 %s -o - | FileCheck -check-prefix=GFX10 %s
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 %s -o - | FileCheck -check-prefix=GFX11 %s
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define amdgpu_kernel void @test(ptr addrspace(1) %src, ptr addrspace(1) %dst) {
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; GFX9-LABEL: test:
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; GFX9: ; %bb.0: ; %entry
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; GFX9-NEXT: s_load_dword s4, s[8:9], 0x1c
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; GFX9-NEXT: s_load_dword s5, s[8:9], 0x38
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; GFX9-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0
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; GFX9-NEXT: s_waitcnt lgkmcnt(0)
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; GFX9-NEXT: s_and_b32 s4, s4, 0xffff
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; GFX9-NEXT: s_mul_i32 s14, s14, s4
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; GFX9-NEXT: s_add_i32 s5, s5, s14
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; GFX9-NEXT: v_add_u32_e32 v1, s5, v0
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; GFX9-NEXT: v_mov_b32_e32 v0, 0
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; GFX9-NEXT: v_ashrrev_i64 v[4:5], 28, v[0:1]
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; GFX9-NEXT: v_mov_b32_e32 v1, s1
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; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s0, v4
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; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v5, vcc
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; GFX9-NEXT: global_load_dwordx4 v[0:3], v[0:1], off
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; GFX9-NEXT: v_mov_b32_e32 v6, s3
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; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, s2, v4
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; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, v6, v5, vcc
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; GFX9-NEXT: s_waitcnt vmcnt(0)
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; GFX9-NEXT: v_not_b32_e32 v3, v3
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; GFX9-NEXT: v_not_b32_e32 v2, v2
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; GFX9-NEXT: v_not_b32_e32 v1, v1
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; GFX9-NEXT: v_not_b32_e32 v0, v0
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; GFX9-NEXT: global_store_dwordx4 v[4:5], v[0:3], off
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; GFX9-NEXT: s_endpgm
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;
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; GFX10-LABEL: test:
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; GFX10: ; %bb.0: ; %entry
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; GFX10-NEXT: s_clause 0x2
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; GFX10-NEXT: s_load_dword s4, s[8:9], 0x1c
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; GFX10-NEXT: s_load_dword s5, s[8:9], 0x38
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; GFX10-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0
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; GFX10-NEXT: v_mov_b32_e32 v1, 0
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; GFX10-NEXT: s_waitcnt lgkmcnt(0)
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; GFX10-NEXT: s_and_b32 s4, s4, 0xffff
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; GFX10-NEXT: s_mul_i32 s14, s14, s4
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; GFX10-NEXT: v_add3_u32 v2, s5, s14, v0
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; GFX10-NEXT: v_ashrrev_i64 v[4:5], 28, v[1:2]
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; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, s0, v4
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; GFX10-NEXT: v_add_co_ci_u32_e64 v1, null, s1, v5, vcc_lo
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; GFX10-NEXT: v_add_co_u32 v4, vcc_lo, s2, v4
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; GFX10-NEXT: v_add_co_ci_u32_e64 v5, null, s3, v5, vcc_lo
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; GFX10-NEXT: global_load_dwordx4 v[0:3], v[0:1], off
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; GFX10-NEXT: s_waitcnt vmcnt(0)
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; GFX10-NEXT: v_not_b32_e32 v3, v3
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; GFX10-NEXT: v_not_b32_e32 v2, v2
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; GFX10-NEXT: v_not_b32_e32 v1, v1
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; GFX10-NEXT: v_not_b32_e32 v0, v0
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; GFX10-NEXT: global_store_dwordx4 v[4:5], v[0:3], off
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; GFX10-NEXT: s_endpgm
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;
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; GFX11-LABEL: test:
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; GFX11: ; %bb.0: ; %entry
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; GFX11-NEXT: s_clause 0x2
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; GFX11-NEXT: s_load_b32 s6, s[4:5], 0x1c
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; GFX11-NEXT: s_load_b32 s7, s[4:5], 0x38
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; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x0
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; GFX11-NEXT: v_and_b32_e32 v1, 0x3ff, v0
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; GFX11-NEXT: v_mov_b32_e32 v0, 0
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; GFX11-NEXT: s_waitcnt lgkmcnt(0)
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; GFX11-NEXT: s_and_b32 s4, s6, 0xffff
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; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
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; GFX11-NEXT: s_mul_i32 s13, s13, s4
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; GFX11-NEXT: v_add3_u32 v1, s7, s13, v1
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; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
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; GFX11-NEXT: v_ashrrev_i64 v[4:5], 28, v[0:1]
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; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, s0, v4
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; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
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; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, s1, v5, vcc_lo
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; GFX11-NEXT: v_add_co_u32 v4, vcc_lo, s2, v4
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; GFX11-NEXT: v_add_co_ci_u32_e64 v5, null, s3, v5, vcc_lo
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; GFX11-NEXT: global_load_b128 v[0:3], v[0:1], off
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; GFX11-NEXT: s_waitcnt vmcnt(0)
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; GFX11-NEXT: v_not_b32_e32 v3, v3
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; GFX11-NEXT: v_not_b32_e32 v2, v2
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; GFX11-NEXT: v_not_b32_e32 v1, v1
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; GFX11-NEXT: v_not_b32_e32 v0, v0
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; GFX11-NEXT: global_store_b128 v[4:5], v[0:3], off
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; GFX11-NEXT: s_endpgm
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entry:
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%implicitarg.ptr = tail call ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()
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%arg.1.ptr = getelementptr inbounds i8, ptr addrspace(4) %implicitarg.ptr, i64 40
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%arg.1 = load i64, ptr addrspace(4) %arg.1.ptr, align 8
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%workgroup.id.x = tail call i32 @llvm.amdgcn.workgroup.id.x()
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%arg.2.ptr = getelementptr inbounds i8, ptr addrspace(4) %implicitarg.ptr, i64 12
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%arg.2 = load i16, ptr addrspace(4) %arg.2.ptr, align 4
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%arg.2.ext = zext i16 %arg.2 to i32
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%mul = mul i32 %workgroup.id.x, %arg.2.ext
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%workitem.id.x = tail call i32 @llvm.amdgcn.workitem.id.x()
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%add = add i32 %mul, %workitem.id.x
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%add.ext = zext i32 %add to i64
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%add.1 = add i64 %arg.1, %add.ext
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%sext = shl i64 %add.1, 32
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%idxprom = ashr exact i64 %sext, 32
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%arrayidx = getelementptr inbounds <16 x i8>, ptr addrspace(1) %src, i64 %idxprom
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%arrayval = load <16 x i8>, ptr addrspace(1) %arrayidx, align 16
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%not = xor <16 x i8> %arrayval, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
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%arrayidx2 = getelementptr inbounds <16 x i8>, ptr addrspace(1) %dst, i64 %idxprom
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store <16 x i8> %not, ptr addrspace(1) %arrayidx2, align 16
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ret void
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}
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