36445f7b8f
On the callee side, `LowerFormalArguments` marks SGPR0-3 as allocated in `CCState` before running the CC analysis. On the caller side, `LowerCall` (and GlobalISel's `lowerCall`/`lowerTailCall`) added the scratch resource to `RegsToPass` without marking it in `CCState`. This caused `CC_AMDGPU_Func` to treat SGPR0-3 as available on the caller side, assigning user inreg args there, while the callee skipped them without marking it in `CCState`. This caused `CC_AMDGPU_Func` to treat SGPR0-3 as available on the caller side, assigning user inreg args there, while the callee skipped them.
79 lines
3.5 KiB
LLVM
79 lines
3.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: not llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs=0 2> %t.err < %s | FileCheck %s
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; RUN: FileCheck -check-prefix=ERR %s < %t.err
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; FIXME: These tests cannot be tail called, and should be executed in a waterfall loop.
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declare hidden void @void_func_i32_inreg(i32 inreg)
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; ERR: error: <unknown>:0:0: in function tail_call_i32_inreg_divergent void (i32): illegal VGPR to SGPR copy
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; ERR: error: <unknown>:0:0: in function indirect_tail_call_i32_inreg_divergent void (i32): illegal VGPR to SGPR copy
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define void @tail_call_i32_inreg_divergent(i32 %vgpr) {
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; CHECK-LABEL: tail_call_i32_inreg_divergent:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CHECK-NEXT: s_mov_b32 s16, s33
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; CHECK-NEXT: s_mov_b32 s33, s32
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; CHECK-NEXT: s_or_saveexec_b64 s[18:19], -1
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; CHECK-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
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; CHECK-NEXT: s_mov_b64 exec, s[18:19]
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; CHECK-NEXT: v_writelane_b32 v40, s16, 2
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; CHECK-NEXT: s_addk_i32 s32, 0x400
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; CHECK-NEXT: v_writelane_b32 v40, s30, 0
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; CHECK-NEXT: v_writelane_b32 v40, s31, 1
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; CHECK-NEXT: s_getpc_b64 s[18:19]
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; CHECK-NEXT: s_add_u32 s18, s18, void_func_i32_inreg@rel32@lo+4
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; CHECK-NEXT: s_addc_u32 s19, s19, void_func_i32_inreg@rel32@hi+12
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; CHECK-NEXT: ; illegal copy v0 to s16
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; CHECK-NEXT: s_swappc_b64 s[30:31], s[18:19]
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; CHECK-NEXT: v_readlane_b32 s31, v40, 1
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; CHECK-NEXT: v_readlane_b32 s30, v40, 0
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; CHECK-NEXT: s_mov_b32 s32, s33
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; CHECK-NEXT: v_readlane_b32 s4, v40, 2
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; CHECK-NEXT: s_or_saveexec_b64 s[6:7], -1
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; CHECK-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
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; CHECK-NEXT: s_mov_b64 exec, s[6:7]
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; CHECK-NEXT: s_mov_b32 s33, s4
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; CHECK-NEXT: s_waitcnt vmcnt(0)
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; CHECK-NEXT: s_setpc_b64 s[30:31]
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tail call void @void_func_i32_inreg(i32 inreg %vgpr)
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ret void
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}
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@constant = external hidden addrspace(4) constant ptr
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define void @indirect_tail_call_i32_inreg_divergent(i32 %vgpr) {
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; CHECK-LABEL: indirect_tail_call_i32_inreg_divergent:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CHECK-NEXT: s_mov_b32 s16, s33
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; CHECK-NEXT: s_mov_b32 s33, s32
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; CHECK-NEXT: s_or_saveexec_b64 s[18:19], -1
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; CHECK-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
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; CHECK-NEXT: s_mov_b64 exec, s[18:19]
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; CHECK-NEXT: s_addk_i32 s32, 0x400
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; CHECK-NEXT: v_writelane_b32 v40, s16, 2
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; CHECK-NEXT: s_getpc_b64 s[16:17]
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; CHECK-NEXT: s_add_u32 s16, s16, constant@rel32@lo+4
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; CHECK-NEXT: s_addc_u32 s17, s17, constant@rel32@hi+12
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; CHECK-NEXT: s_load_dwordx2 s[18:19], s[16:17], 0x0
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; CHECK-NEXT: v_writelane_b32 v40, s30, 0
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; CHECK-NEXT: v_writelane_b32 v40, s31, 1
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; CHECK-NEXT: ; illegal copy v0 to s16
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; CHECK-NEXT: s_waitcnt lgkmcnt(0)
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; CHECK-NEXT: s_swappc_b64 s[30:31], s[18:19]
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; CHECK-NEXT: v_readlane_b32 s31, v40, 1
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; CHECK-NEXT: v_readlane_b32 s30, v40, 0
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; CHECK-NEXT: s_mov_b32 s32, s33
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; CHECK-NEXT: v_readlane_b32 s4, v40, 2
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; CHECK-NEXT: s_or_saveexec_b64 s[6:7], -1
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; CHECK-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
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; CHECK-NEXT: s_mov_b64 exec, s[6:7]
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; CHECK-NEXT: s_mov_b32 s33, s4
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; CHECK-NEXT: s_waitcnt vmcnt(0)
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; CHECK-NEXT: s_setpc_b64 s[30:31]
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%fptr = load ptr, ptr addrspace(4) @constant, align 8
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tail call void %fptr(i32 inreg %vgpr)
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ret void
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}
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