56ce7ed72b
Some of the MIR test hit a bug where it errors if there is a raw global reference as the referenced value. Worked around some of those by just keeping a no-op bitcast constant expression.
197 lines
6.4 KiB
LLVM
197 lines
6.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc -mtriple=bpfel -mattr=+allows-misaligned-mem-access -verify-machineinstrs %s -o - \
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; RUN: | FileCheck --check-prefixes=ALL,MISALIGN %s
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; RUN: llc -mtriple=bpfeb -mattr=+allows-misaligned-mem-access -verify-machineinstrs %s -o - \
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; RUN: | FileCheck --check-prefixes=ALL,MISALIGN %s
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; RUN: llc -mtriple=bpfel -verify-machineinstrs %s -o - \
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; RUN: | FileCheck --check-prefixes=ALL,ALIGN %s
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; RUN: llc -mtriple=bpfeb -verify-machineinstrs %s -o - \
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; RUN: | FileCheck --check-prefixes=ALL,ALIGN %s
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; NOTE:
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; This test verifies that the new +bpf-allow-misaligned-mem-access
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; feature allows the BPF backend to emit direct unaligned load/store
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; instructions instead of byte-by-byte emulation sequences.
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; ---------------------------------------------------------------------
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; i8 load
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; ---------------------------------------------------------------------
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define i8 @test_load_i8(ptr %p) {
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; ALL-LABEL: test_load_i8:
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; ALL: # %bb.0:
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; ALL-NEXT: w{{[0-9]+}} = *(u8 *)(r1 + 0)
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; ALL-NEXT: exit
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%v = load i8, ptr %p, align 1
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ret i8 %v
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}
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; ---------------------------------------------------------------------
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; i8 store
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; ---------------------------------------------------------------------
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define void @test_store_i8(ptr %p, i8 %v) {
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; ALL-LABEL: test_store_i8:
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; ALL: # %bb.0:
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; ALL-NEXT: *(u8 *)(r1 + 0) = w{{[0-9]+}}
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; ALL-NEXT: exit
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store i8 %v, ptr %p, align 1
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ret void
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}
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; ---------------------------------------------------------------------
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; i16 load
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; ---------------------------------------------------------------------
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define i16 @test_load_i16(ptr %p) {
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; MISALIGN-LABEL: test_load_i16:
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; MISALIGN: # %bb.0:
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; MISALIGN: w{{[0-9]+}} = *(u16 *)(r1 + 0)
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; MISALIGN: exit
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;
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; ALIGN-LABEL: test_load_i16:
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; ALIGN: # %bb.0:
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; ALIGN-DAG: w{{[0-9]+}} = *(u8 *)(r1 + 0)
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; ALIGN-DAG: w{{[0-9]+}} = *(u8 *)(r1 + 1)
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; ALIGN-DAG: w{{[0-9]+}} <<= 8
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; ALIGN-DAG: w{{[0-9]+}} |= w{{[0-9]+}}
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; ALIGN: exit
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%v = load i16, ptr %p, align 1
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ret i16 %v
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}
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; ---------------------------------------------------------------------
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; i16 store
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; ---------------------------------------------------------------------
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define void @test_store_i16(ptr %p, i16 %v) {
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; MISALIGN-LABEL: test_store_i16:
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; MISALIGN: # %bb.0:
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; MISALIGN: *(u16 *)(r1 + 0) = w{{[0-9]+}}
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; MISALIGN: exit
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;
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; ALIGN-LABEL: test_store_i16:
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; ALIGN: # %bb.0:
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; ALIGN-DAG: *(u8 *)(r1 + 0) = w{{[0-9]+}}
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; ALIGN-DAG: w{{[0-9]+}} >>= 8
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; ALIGN-DAG: *(u8 *)(r1 + 1) = w{{[0-9]+}}
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; ALIGN: exit
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store i16 %v, ptr %p, align 1
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ret void
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}
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; ---------------------------------------------------------------------
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; i32 load
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; ---------------------------------------------------------------------
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define i32 @test_load_i32(ptr %p) {
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; MISALIGN-LABEL: test_load_i32:
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; MISALIGN: # %bb.0:
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; MISALIGN: w{{[0-9]+}} = *(u32 *)(r1 + 0)
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; MISALIGN: exit
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;
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; ALIGN-LABEL: test_load_i32:
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; ALIGN: # %bb.0:
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; ALIGN-DAG: w{{[0-9]+}} = *(u8 *)(r1 + 0)
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; ALIGN-DAG: w{{[0-9]+}} <<= 8
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; ALIGN-DAG: w{{[0-9]+}} = *(u8 *)(r1 + 1)
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; ALIGN-DAG: w{{[0-9]+}} |= w{{[0-9]+}}
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; ALIGN-DAG: w{{[0-9]+}} = *(u8 *)(r1 + 2)
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; ALIGN-DAG: w{{[0-9]+}} <<= 16
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; ALIGN-DAG: w{{[0-9]+}} = *(u8 *)(r1 + 3)
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; ALIGN-DAG: w{{[0-9]+}} <<= 24
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; ALIGN: exit
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%v = load i32, ptr %p, align 1
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ret i32 %v
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}
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; ---------------------------------------------------------------------
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; i32 store
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; ---------------------------------------------------------------------
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define void @test_store_i32(ptr %p, i32 %v) {
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; MISALIGN-LABEL: test_store_i32:
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; MISALIGN: # %bb.0:
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; MISALIGN: *(u32 *)(r1 + 0) = w{{[0-9]+}}
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; MISALIGN: exit
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;
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; ALIGN-LABEL: test_store_i32:
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; ALIGN: # %bb.0:
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; ALIGN-DAG: w{{[0-9]+}} = w{{[0-9]+}}
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; ALIGN-DAG: w{{[0-9]+}} >>= 24
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; ALIGN-DAG: *(u8 *)(r1 + 0) = w{{[0-9]+}}
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; ALIGN-DAG: w{{[0-9]+}} = w{{[0-9]+}}
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; ALIGN-DAG: w{{[0-9]+}} >>= 16
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; ALIGN-DAG: *(u8 *)(r1 + 1) = w{{[0-9]+}}
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; ALIGN-DAG: *(u8 *)(r1 + 2) = w{{[0-9]+}}
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; ALIGN-DAG: w{{[0-9]+}} >>= 8
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; ALIGN-DAG: *(u8 *)(r1 + 3) = w{{[0-9]+}}
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; ALIGN: exit
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store i32 %v, ptr %p, align 1
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ret void
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}
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; ---------------------------------------------------------------------
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; i64 load
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; ---------------------------------------------------------------------
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define i64 @test_load_i64(ptr %p) {
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; MISALIGN-LABEL: test_load_i64:
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; MISALIGN: # %bb.0:
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; MISALIGN: r0 = *(u64 *)(r1 + 0)
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; MISALIGN: exit
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;
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; ALIGN-LABEL: test_load_i64:
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; ALIGN: # %bb.0:
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; ALIGN-DAG: w{{[0-9]+}} = *(u8 *)(r1 + 0)
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; ALIGN-DAG: w{{[0-9]+}} = *(u8 *)(r1 + 1)
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; ALIGN-DAG: r{{[0-9]+}} <<= 8
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; ALIGN-DAG: r{{[0-9]+}} |= r{{[0-9]+}}
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; ALIGN-DAG: w{{[0-9]+}} = *(u8 *)(r1 + 2)
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; ALIGN-DAG: r{{[0-9]+}} <<= 16
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; ALIGN-DAG: w{{[0-9]+}} = *(u8 *)(r1 + 3)
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; ALIGN-DAG: r{{[0-9]+}} <<= 24
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; ALIGN-DAG: w{{[0-9]+}} = *(u8 *)(r1 + 4)
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; ALIGN-DAG: w{{[0-9]+}} <<= 8
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; ALIGN-DAG: w{{[0-9]+}} = *(u8 *)(r1 + 5)
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; ALIGN-DAG: w{{[0-9]+}} |= w{{[0-9]+}}
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; ALIGN-DAG: w{{[0-9]+}} = *(u8 *)(r1 + 6)
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; ALIGN-DAG: w{{[0-9]+}} <<= 16
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; ALIGN-DAG: w{{[0-9]+}} = *(u8 *)(r1 + 7)
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; ALIGN-DAG: w{{[0-9]+}} <<= 24
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; ALIGN-DAG: r{{[0-9]+}} <<= 32
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; ALIGN: exit
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%v = load i64, ptr %p, align 1
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ret i64 %v
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}
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; ---------------------------------------------------------------------
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; i64 store
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; ---------------------------------------------------------------------
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define void @test_store_i64(ptr %p, i64 %v) {
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; MISALIGN-LABEL: test_store_i64:
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; MISALIGN: # %bb.0:
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; MISALIGN: *(u64 *)(r1 + 0) = r2
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; MISALIGN: exit
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;
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; ALIGN-LABEL: test_store_i64:
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; ALIGN: # %bb.0:
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; ALIGN-DAG: *(u8 *)(r1 + 0) = w{{[0-9]+}}
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; ALIGN-DAG: r{{[0-9]+}} = r{{[0-9]+}}
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; ALIGN-DAG: r{{[0-9]+}} >>= 56
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; ALIGN-DAG: *(u8 *)(r1 + 1) = w{{[0-9]+}}
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; ALIGN-DAG: r{{[0-9]+}} >>= 48
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; ALIGN-DAG: *(u8 *)(r1 + 2) = w{{[0-9]+}}
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; ALIGN-DAG: r{{[0-9]+}} >>= 40
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; ALIGN-DAG: *(u8 *)(r1 + 3) = w{{[0-9]+}}
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; ALIGN-DAG: r{{[0-9]+}} >>= 32
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; ALIGN-DAG: *(u8 *)(r1 + 4) = w{{[0-9]+}}
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; ALIGN-DAG: r{{[0-9]+}} >>= 24
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; ALIGN-DAG: *(u8 *)(r1 + 5) = w{{[0-9]+}}
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; ALIGN-DAG: r{{[0-9]+}} >>= 16
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; ALIGN-DAG: *(u8 *)(r1 + 6) = w{{[0-9]+}}
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; ALIGN-DAG: r{{[0-9]+}} >>= 8
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; ALIGN-DAG: *(u8 *)(r1 + 7) = w{{[0-9]+}}
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; ALIGN: exit
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store i64 %v, ptr %p, align 1
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ret void
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}
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