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llvm-project/llvm/test/CodeGen/NVPTX
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Alex MacLean 91dbaf5d89
[NVPTX] Print param space sub-qualifiers where supported (#187350) 
Print param space sub-qualifiers (`param::entry` and `param::func`) for
PTX 8.3+, as described in the [PTX ISA
docs](https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#parameter-state-space).
This requires threading the `MCSubtargetInfo` through the inst printer,
which is done by setting `PassSubtarget = 1` on the asm writer.

Emitting the full space avoids the need for ptxas to infer it, improving
readability and more importantly preventing potential bugs if valid LLVM
IR transformations were to move a load from ADDRESS_SPACE_ENTRY_PARAM
into a device function.
2026-03-20 20:44:56 -07:00
..
access-non-generic.ll
…
activemask.ll
…
add-sub-128bit.ll
…
addr-mode.ll
…
addrspacecast-cse.ll
…
addrspacecast-folding.ll
…
addrspacecast-gvar.ll
…
addrspacecast-ptx64.ll
…
addrspacecast.ll
…
aggr-param.ll
…
aggregate-return.ll
…
alias-errors.ll
…
alias.ll
…
and-or-setcc.ll
…
annotations.ll
…
anonymous-fn-param.ll
…
APIntLoadStore.ll
…
APIntParam.ll
…
APIntSextParam.ll
…
APIntZextParam.ll
…
applypriority.ll
…
arbitrary-fp-to-float.ll
[SelectionDAG] Add expansion for llvm.convert.from.arbitrary.fp (#179318)
2026-03-04 10:40:47 +01:00
arg-lowering.ll
…
arithmetic-fp-sm20.ll
…
arithmetic-int.ll
…
async-copy.ll
…
atomic-lower-local.ll
…
atomicrmw-expand.err.ll
…
atomicrmw-sm60.ll
Reland "[NVPTX][AtomicExpandPass] Complete support for AtomicRMW in NVPTX (#176015)" (#179553)
2026-02-04 16:15:49 -08:00
atomicrmw-sm70.ll
Reland "[NVPTX][AtomicExpandPass] Complete support for AtomicRMW in NVPTX (#176015)" (#179553)
2026-02-04 16:15:49 -08:00
atomicrmw-sm90.ll
Reland "[NVPTX][AtomicExpandPass] Complete support for AtomicRMW in NVPTX (#176015)" (#179553)
2026-02-04 16:15:49 -08:00
atomicrmw.py
Reland "[NVPTX][AtomicExpandPass] Complete support for AtomicRMW in NVPTX (#176015)" (#179553)
2026-02-04 16:15:49 -08:00
atomics-b128.ll
Reland "[RegAlloc] Fix the terminal rule check for interfere with DstReg (#168661)" (#169219)
2025-11-24 09:27:25 +08:00
atomics-sm60.ll
Reland "[NVPTX][AtomicExpandPass] Complete support for AtomicRMW in NVPTX (#176015)" (#179553)
2026-02-04 16:15:49 -08:00
atomics-with-scope.ll
…
atomics.ll
[NVPTX][AutoUpgrade] atom.load intrinsics should be autoupgraded to monotonic atomicrmw for NVPTX (#187140)
2026-03-18 01:26:47 +00:00
b52037.ll
…
barrier.ll
[NVPTX] Add missing type suffixes for barrier.cta.red (#172945)
2025-12-19 05:53:49 -08:00
bf16-instructions.ll
Reapply "DAG: Allow select ptr combine for non-0 address spaces" (#168292) (#168786)
2025-11-20 12:13:46 -05:00
bf16.ll
…
bf16x2-instructions-approx.ll
…
bf16x2-instructions.ll
Reapply "DAG: Allow select ptr combine for non-0 address spaces" (#168292) (#168786)
2025-11-20 12:13:46 -05:00
bfe.ll
…
blocksareclusters-kernel-attr.ll
…
bmsk.ll
…
boolean-patterns.ll
…
branch-fold.ll
…
branch-fold.mir
…
brkpt.ll
…
bswap.ll
[NVPTX] Use PRMT instruction to lower i16 bswap (#168968)
2025-11-24 16:11:05 -08:00
bug17709.ll
…
bug21465.ll
[NVPTX] Cleanup NVPTXLowerArgs, simplifying logic and improving alignment propagation (#180286)
2026-02-20 09:40:21 -08:00
bug22246.ll
Reapply "DAG: Allow select ptr combine for non-0 address spaces" (#168292) (#168786)
2025-11-20 12:13:46 -05:00
bug22322.ll
…
bug26185-2.ll
…
bug26185.ll
…
bug41651.ll
…
bug52623.ll
…
bypass-div.ll
…
byval-arg-vectorize.ll
…
byval-const-global.ll
…
call_bitcast_byval.ll
…
call-with-alloca-buffer.ll
…
callchain.ll
…
calling-conv.ll
…
calls-with-phi.ll
…
chain-different-as.ll
…
cluster-dim.ll
…
clusterlaunchcontrol-multicast.ll
Reland "[NVPTX] Validate user-specified PTX version against SM version" (#180116)
2026-02-10 18:11:54 +00:00
clusterlaunchcontrol.ll
…
cmpxchg-sm60.ll
[NVPTX][NFC] Update fence.py and cmpxchg.py to generate ptxas-sm_XY and ptxas-isa-X.Y checks in RUN lines (#179378)
2026-02-04 08:50:55 -08:00
cmpxchg-sm70.ll
[NVPTX][NFC] Update fence.py and cmpxchg.py to generate ptxas-sm_XY and ptxas-isa-X.Y checks in RUN lines (#179378)
2026-02-04 08:50:55 -08:00
cmpxchg-sm90.ll
[NVPTX][NFC] Update fence.py and cmpxchg.py to generate ptxas-sm_XY and ptxas-isa-X.Y checks in RUN lines (#179378)
2026-02-04 08:50:55 -08:00
cmpxchg-unsupported-syncscope.err.ll
[test] Avoid writing test output to readonly dir (#166404)
2025-11-04 17:54:43 +00:00
cmpxchg.ll
…
cmpxchg.py
[NVPTX][NFC] Update fence.py and cmpxchg.py to generate ptxas-sm_XY and ptxas-isa-X.Y checks in RUN lines (#179378)
2026-02-04 08:50:55 -08:00
combine-mad.ll
…
combine-min-max.ll
…
combine-mul-wide-type.ll
[NVPTX] Use correct mul.wide operand type when matching on shl in combineMulWide (#168986)
2026-01-08 09:27:40 -08:00
combine-wide.ll
…
common-linkage.ll
…
compare-int.ll
…
compute-ptx-value-vts.ll
…
constant-vectors.ll
…
convergent-mir-call.ll
…
convert_fp4x2_sm_100f.ll
[NVPTX] Add intrinsics for new narrow FP conversions (#173954)
2026-02-19 11:19:10 +05:30
convert_fp6x2_sm_100f.ll
[NVPTX] Add intrinsics for new narrow FP conversions (#173954)
2026-02-19 11:19:10 +05:30
convert_fp8x2_sm_100f.ll
[NVPTX] Add intrinsics for new narrow FP conversions (#173954)
2026-02-19 11:19:10 +05:30
convert_s2f6x2_sm_100a.ll
[NVPTX] Add intrinsics for new narrow FP conversions (#173954)
2026-02-19 11:19:10 +05:30
convert-call-to-indirect.ll
…
convert-fp-i8.ll
…
convert-fp.ll
…
convert-int-sm20.ll
…
convert-sm80-sf.ll
[clang][NVPTX] Add remaining float to fp16 conversions (#167641)
2025-11-19 13:03:33 +05:30
convert-sm80.ll
[clang][NVPTX] Add remaining float to fp16 conversions (#167641)
2025-11-19 13:03:33 +05:30
convert-sm89.ll
[clang][NVPTX] Fix SM requirement of f32-tf32 rna satfinite conversion (#167836)
2025-11-18 09:29:10 +05:30
convert-sm90.ll
…
convert-sm100.ll
…
convert-sm100a.ll
Reland "[NVPTX] Validate user-specified PTX version against SM version" (#180116)
2026-02-10 18:11:54 +00:00
convert-sm103a.ll
Reland "[NVPTX] Validate user-specified PTX version against SM version" (#180116)
2026-02-10 18:11:54 +00:00
copysign.ll
…
cp-async-bulk-ptx86.ll
[NVPTX] Add TMA non-tensor variant of g2s-cta intrinsic (#167508)
2025-11-13 15:33:46 +05:30
cp-async-bulk-s2g-sm100.ll
…
cp-async-bulk-tensor-g2s-1cta.ll
[NVPTX] Move TMA G2S lowering to Tablegen (#165710)
2025-10-31 18:54:43 +05:30
cp-async-bulk-tensor-g2s-2cta.ll
[NVPTX] Move TMA G2S lowering to Tablegen (#165710)
2025-10-31 18:54:43 +05:30
cp-async-bulk-tensor-g2s-cta-sm90.ll
…
cp-async-bulk-tensor-g2s-cta-sm100.ll
…
cp-async-bulk-tensor-g2s-cta-sm100a.ll
…
cp-async-bulk-tensor-g2s-gather4.ll
[NVPTX] Move TMA G2S lowering to Tablegen (#165710)
2025-10-31 18:54:43 +05:30
cp-async-bulk-tensor-g2s-im2colw128.ll
[NVPTX] Move TMA G2S lowering to Tablegen (#165710)
2025-10-31 18:54:43 +05:30
cp-async-bulk-tensor-g2s-im2colw.ll
[NVPTX] Move TMA G2S lowering to Tablegen (#165710)
2025-10-31 18:54:43 +05:30
cp-async-bulk-tensor-g2s-invalid.ll
…
cp-async-bulk-tensor-g2s.ll
[NVPTX] Move TMA G2S lowering to Tablegen (#165710)
2025-10-31 18:54:43 +05:30
cp-async-bulk-tensor-prefetch-sm100a.ll
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cp-async-bulk-tensor-prefetch.ll
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cp-async-bulk-tensor-reduce.ll
…
cp-async-bulk-tensor-s2g-scatter4.ll
…
cp-async-bulk-tensor-s2g.ll
…
cp-async-bulk.ll
…
cse-mov-sym.ll
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ctlz.ll
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ctpop.ll
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cttz.ll
…
dag-cse.ll
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default-sm.ll
[NVPTX] Update the default SM to 7.5 (#176021)
2026-01-22 18:26:55 +00:00
demote-vars.ll
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disable-opt.ll
…
discard.ll
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disjoint-or-addr.ll
[InferAS] Infer the address space of inttoptr (#173244)
2026-02-20 09:49:00 +08:00
distributed-shared-cluster.ll
Reland "[NVPTX][AtomicExpandPass] Complete support for AtomicRMW in NVPTX (#176015)" (#179553)
2026-02-04 16:15:49 -08:00
div-ri.ll
…
div.ll
IR: Promote "denormal-fp-math" to a first class attribute (#174293)
2026-02-05 13:31:26 +00:00
divrem-combine.ll
…
dot-product.ll
…
dynamic_stackalloc.ll
…
dynamic-stackalloc-regression.ll
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elect.ll
…
empty-type.ll
…
envreg.ll
…
extern-shared-valid-name.ll
[NVPTX] fix illegal name for .extern .shared global variables (#173018)
2026-01-22 21:28:07 +01:00
extloadv.ll
…
extractelement.ll
…
f16-abs.ll
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f16-add-sat.ll
[clang][NVPTX] Add missing half-precision add/mul/fma intrinsics (#170079)
2026-01-20 17:56:55 +05:30
f16-ex2.ll
[NVPTX] Add ex2.approx bf16 support and cleanup intrinsic definition (#165446)
2025-11-01 17:51:17 +00:00
f16-instructions.ll
fix llvm.fma.f16 double rounding issue when there is no native support (#171904)
2025-12-17 22:03:01 +01:00
f16-mul-sat.ll
[clang][NVPTX] Add missing half-precision add/mul/fma intrinsics (#170079)
2026-01-20 17:56:55 +05:30
f16-sub-sat.ll
[clang][NVPTX] Add missing half-precision add/mul/fma intrinsics (#170079)
2026-01-20 17:56:55 +05:30
f16x2-instructions.ll
fix llvm.fma.f16 double rounding issue when there is no native support (#171904)
2025-12-17 22:03:01 +01:00
f32-ex2.ll
Reland "[NVPTX] Validate user-specified PTX version against SM version" (#180116)
2026-02-10 18:11:54 +00:00
f32-lg2.ll
…
f32x2-convert-i32x2.ll
…
f32x2-instructions.ll
IR: Promote "denormal-fp-math" to a first class attribute (#174293)
2026-02-05 13:31:26 +00:00
fabs-intrinsics.ll
…
fast-math.ll
IR: Promote "denormal-fp-math" to a first class attribute (#174293)
2026-02-05 13:31:26 +00:00
fcos-no-fast-math.ll
…
fence-proxy-sm90-ptx86.ll
[NVPTX] Add a few more missing fence intrinsics (#166352)
2025-11-19 06:50:54 +05:30
fence-proxy-sm90.ll
[NVPTX] Add a few more missing fence intrinsics (#166352)
2025-11-19 06:50:54 +05:30
fence-proxy-tensormap-invalid.ll
[NVPTX] Add a few more missing fence intrinsics (#166352)
2025-11-19 06:50:54 +05:30
fence-proxy-tensormap.ll
…
fence-proxy.ll
[NVPTX] Add a few more missing fence intrinsics (#166352)
2025-11-19 06:50:54 +05:30
fence.ll
[NVPTX] Fix scoped atomic when given runtime values (#185883)
2026-03-17 16:28:02 -05:00
fence.py
[NVPTX] Fix scoped atomic when given runtime values (#185883)
2026-03-17 16:28:02 -05:00
fexp2.ll
Reland "[NVPTX] Validate user-specified PTX version against SM version" (#180116)
2026-02-10 18:11:54 +00:00
filetype-null.ll
…
flo.ll
…
flog2.ll
Reland "[NVPTX] Validate user-specified PTX version against SM version" (#180116)
2026-02-10 18:11:54 +00:00
fma-assoc.ll
[CodeGen] Remove -enable-unsafe-fp-math option (#164559)
2025-10-22 15:40:31 +08:00
fma-disable.ll
…
fma-oob.ll
[clang][NVPTX] Add missing half-precision add/mul/fma intrinsics (#170079)
2026-01-20 17:56:55 +05:30
fma-relu-contract.ll
[NVPTX] Remove NoNaNsFPMath uses (#183447)
2026-03-05 20:50:05 +08:00
fma-relu-fma-intrinsic.ll
…
fma-relu-instruction-flag.ll
…
fma.ll
…
fmax3.ll
…
fminimum-fmaximum.ll
…
fns.ll
…
fold-movs.ll
…
forward-ld-param.ll
…
fp128-storage-type.ll
…
fp-arith-sat.ll
[clang][NVPTX] Add support for mixed-precision FP arithmetic (#168359)
2025-12-15 16:28:23 +05:30
fp-contract-f32x2.ll
…
fp-contract.ll
…
fp-fold-sub.ll
[clang][NVPTX] Add support for mixed-precision FP arithmetic (#168359)
2025-12-15 16:28:23 +05:30
fp-literals.ll
…
frameindex-lifetime.ll
…
frem.ll
…
fsin-no-fast-math.ll
…
function-align.ll
…
funnel-shift-clamp.ll
…
generic-to-nvvm-ir.ll
…
generic-to-nvvm.ll
…
global-addrspace.ll
…
global-ctor-empty.ll
…
global-incomplete-init.ll
…
global-ordering.ll
…
global-variable-big.ll
…
global-visibility.ll
…
globals_init.ll
…
globals_lowering.ll
…
griddepcontrol.ll
…
gvar-init.ll
…
half.ll
…
i1-array-global.ll
…
i1-ext-load.ll
[DAG] Fold (X +/- Y) & Y --> ~X & Y when Y is a power of 2 (or zero). (#181677)
2026-02-18 12:19:21 +00:00
i1-global.ll
…
i1-icmp.ll
…
i1-int-to-fp.ll
…
i1-load-lower.ll
…
i1-param.ll
…
i1-select.ll
Reapply "DAG: Allow select ptr combine for non-0 address spaces" (#168292) (#168786)
2025-11-20 12:13:46 -05:00
i8-param.ll
…
i8x2-instructions.ll
…
i8x4-instructions.ll
Reapply "DAG: Allow select ptr combine for non-0 address spaces" (#168292) (#168786)
2025-11-20 12:13:46 -05:00
i16x2-instructions.ll
[DAG] visitOR - attempt to fold (or buildvector(), buildvector()) -> buildvector() (#183032)
2026-02-25 10:03:15 +00:00
i32x2-instructions.ll
…
i128-array.ll
…
i128-global.ll
…
i128-ld-st.ll
…
i128-param.ll
…
i128-retval.ll
…
i128-struct.ll
…
i128.ll
Reland "[NVPTX] Validate user-specified PTX version against SM version" (#180116)
2026-02-10 18:11:54 +00:00
idioms.ll
…
imad.ll
…
indirect_byval.ll
…
inline-asm-b128-test1.ll
[NVPTX] Print param space sub-qualifiers where supported (#187350)
2026-03-20 20:44:56 -07:00
inline-asm-b128-test2.ll
…
inline-asm-b128-test3.ll
…
inline-asm.ll
…
inlineasm-output-template.ll
…
insertelt-dynamic.ll
[DAGCombiner] Lower dynamic insertelt chain more efficiently (#162368)
2025-10-29 09:46:01 -07:00
intr-range.ll
…
intrinsic-old.ll
…
intrinsics-sm90-ptx81.ll
[MLIR][NVPTX] Add intrinsics and Ops to read smem-sizes (#173089)
2025-12-21 19:29:24 +05:30
intrinsics-sm90.ll
…
intrinsics.ll
[MLIR][NVPTX] Add intrinsics and Ops to read smem-sizes (#173089)
2025-12-21 19:29:24 +05:30
isspacep.ll
…
jump-table.ll
[NVPTX] Fixup and refactor brx.idx support (#171933)
2025-12-12 11:36:15 -08:00
kernel-param-align.ll
…
ld-addrspace.ll
…
ld-generic.ll
…
ld-param-sink.ll
…
ld-st-addrrspace.py
…
ldg-invariant-256.ll
[NVPTX] Lower LLVM masked vector loads and stores to PTX (#159387)
2025-11-25 10:26:15 -06:00
ldg-invariant.ll
…
ldparam-v4.ll
…
ldu-i8.ll
…
ldu-ldg.ll
…
ldu-reg-plus-offset.ll
…
lit.local.cfg
Reland "[NVPTX][AtomicExpandPass] Complete support for AtomicRMW in NVPTX (#176015)" (#179553)
2026-02-04 16:15:49 -08:00
load-sext-i1.ll
…
load-store-256-addressing-invariant.ll
…
load-store-256-addressing.ll
…
load-store-atomic.err.ll
…
load-store-scalars.ll
…
load-store-sm-70.ll
…
load-store-sm-90.ll
…
load-store-vectors-256.ll
…
load-store-vectors.ll
…
load-with-non-coherent-cache.ll
…
LoadStoreVectorizer.ll
[NVPTX] Update the default SM to 7.5 (#176021)
2026-01-22 18:26:55 +00:00
local-stack-frame.ll
…
loop-vectorize.ll
…
lower-aggr-copies.ll
[LowerMemIntrinsics] Optimize memset lowering (#169040)
2026-02-04 13:35:13 +01:00
lower-alloca.ll
…
lower-args-alignment.ll
[NVPTX] Cleanup NVPTXLowerArgs, simplifying logic and improving alignment propagation (#180286)
2026-02-20 09:40:21 -08:00
lower-args-gridconstant.ll
[NVPTX] Cleanup NVPTXLowerArgs, simplifying logic and improving alignment propagation (#180286)
2026-02-20 09:40:21 -08:00
lower-args.ll
[NVPTX] Refactor NVPTXLowerArgs and move helpers to NVPTXUtilities (#183686)
2026-03-02 10:30:36 -08:00
lower-byval-args.ll
[AMDGPU] Make uniform-work-group-size a valueless attribute (#183925)
2026-03-01 21:29:55 +00:00
lower-ctor-dtor.ll
[NVPTXCtorDtorLowering] Removing unnecessary pointer arithmetic (#182269)
2026-02-19 16:02:23 +01:00
lower-kernel-ptr-arg.ll
[NVPTX] Refactor NVPTXLowerArgs and move helpers to NVPTXUtilities (#183686)
2026-03-02 10:30:36 -08:00
machine-sink.ll
…
machinelicm-no-preheader.mir
[NVPTX] Lower LLVM masked vector loads and stores to PTX (#159387)
2025-11-25 10:26:15 -06:00
MachineSink-call.ll
…
MachineSink-convergent.ll
…
managed.ll
…
mark-kernel-ptrs-global.ll
[NVPTX] Refactor NVPTXLowerArgs and move helpers to NVPTXUtilities (#183686)
2026-03-02 10:30:36 -08:00
masked-load-3xhalf.ll
[LoadStoreVectorizer] Fill gaps in load/store chains to enable vectorization (#159388)
2025-12-08 15:57:17 -06:00
masked-load-vectors.ll
[NVPTX] Fix lit test issues from masked load/store implementation (#169535)
2025-11-25 12:27:31 -06:00
masked-store-variable-mask.ll
[NVPTX] Fix lit test issues from masked load/store implementation (#169535)
2025-11-25 12:27:31 -06:00
masked-store-vectors-256.ll
[NVPTX] Fix lit test issues from masked load/store implementation (#169535)
2025-11-25 12:27:31 -06:00
match.ll
…
math-intrins-sm53-ptx42.ll
…
math-intrins-sm80-ptx70-autoupgrade.ll
…
math-intrins-sm80-ptx70-instcombine.ll
IR: Promote "denormal-fp-math" to a first class attribute (#174293)
2026-02-05 13:31:26 +00:00
math-intrins-sm80-ptx70.ll
…
math-intrins-sm86-ptx72-autoupgrade.ll
…
math-intrins-sm86-ptx72.ll
…
math-intrins.ll
IR: Promote "denormal-fp-math" to a first class attribute (#174293)
2026-02-05 13:31:26 +00:00
max-align.ll
…
maxclusterrank.ll
…
mbarrier_arr_relaxed.ll
[NVPTX] Add missing mbarrier intrinsics (#164864)
2025-10-27 14:23:40 +05:30
mbarrier_arr.ll
[NVPTX] Add missing mbarrier intrinsics (#164864)
2025-10-27 14:23:40 +05:30
mbarrier_tx.ll
[NVPTX] Add missing mbarrier intrinsics (#164864)
2025-10-27 14:23:40 +05:30
mbarrier_wait_sm80_ptx70.ll
[NVPTX] Add missing mbarrier intrinsics (#164864)
2025-10-27 14:23:40 +05:30
mbarrier_wait_sm80_ptx71.ll
[NVPTX] Add missing mbarrier intrinsics (#164864)
2025-10-27 14:23:40 +05:30
mbarrier_wait_sm90_ptx78.ll
[NVPTX] Add missing mbarrier intrinsics (#164864)
2025-10-27 14:23:40 +05:30
mbarrier_wait_sm90_ptx80.ll
[NVPTX] Add missing mbarrier intrinsics (#164864)
2025-10-27 14:23:40 +05:30
mbarrier_wait_sm90_ptx86.ll
[NVPTX] Add missing mbarrier intrinsics (#164864)
2025-10-27 14:23:40 +05:30
mbarrier.ll
…
minmax-negative.ll
…
misaligned-vector-ldst.ll
…
misched_func_call.ll
…
mixed-precision-fp.ll
[clang][NVPTX] Add support for mixed-precision FP arithmetic (#168359)
2025-12-15 16:28:23 +05:30
mma-no-sink-after-laneid-check.ll
…
module-inline-asm.ll
…
mulhi-intrins.ll
…
mulwide.ll
…
naked-fn-with-frame-pointer.ll
…
nanosleep.ll
…
no-extra-parens.ll
…
no-f32x2.ll
…
no-stack-protector-libcall-error.ll
StackProtector: Use LibcallLoweringInfo analysis (#170329)
2026-01-18 07:12:17 +01:00
noduplicate-syncthreads.ll
…
nofunc.ll
…
noreturn.ll
…
nounroll.ll
…
nvcl-param-align.ll
…
nvptx-aa-inline-asm.ll
…
nvptx-aa.ll
…
nvptx-fold-fma.ll
[NVPTX] Add IR pass for FMA transformation in the llc pipeline (#154735)
2025-12-09 22:39:11 +05:30
nvptx-prec-divf32-flag.ll
IR: Promote "denormal-fp-math" to a first class attribute (#174293)
2026-02-05 13:31:26 +00:00
NVPTXAA_before_BasicAA.ll
…
nvvm-annotations-D120129.ll
…
nvvm-reflect-arch-O0.ll
Reland "[NVPTX] Validate user-specified PTX version against SM version" (#180116)
2026-02-10 18:11:54 +00:00
nvvm-reflect-arch.ll
…
nvvm-reflect-module-flag.ll
…
nvvm-reflect-ocl.ll
…
nvvm-reflect-opaque.ll
…
nvvm-reflect-options.ll
…
nvvm-reflect.ll
…
op-fence.ll
[NVPTX] Add a few more missing fence intrinsics (#166352)
2025-11-19 06:50:54 +05:30
packed-aggr.ll
…
param-add.ll
[Support] Support debug counters in non-assertion builds (#170468)
2025-12-03 16:21:47 +01:00
param-align.ll
…
param-load-store.ll
…
param-overalign.ll
…
param-space-subqualifiers.ll
[NVPTX] Print param space sub-qualifiers where supported (#187350)
2026-03-20 20:44:56 -07:00
param-vectorize-device.ll
[NVPTX] Fix lit test issue from used_bytes_mask (#171220)
2025-12-08 19:35:02 -06:00
param-vectorize-kernel.ll
…
pass-name.ll
…
pm-event.ll
[NVPTX] Print PM Event Mask value as unsigned integer. (#178891)
2026-02-03 07:49:58 +01:00
pow2_mask_cmp.ll
…
pr13291-i1-store.ll
…
pr16278.ll
…
pr17529.ll
…
pr126337.ll
…
prefetch-inferas-test.ll
…
prefetch.ll
…
prmt-const-folding.ll
…
prmt.ll
…
proxy-reg-erasure-ptx.ll
…
proxy-reg-erasure.mir
[NVPTX] Lower LLVM masked vector loads and stores to PTX (#159387)
2025-11-25 10:26:15 -06:00
ptx-version-validation.ll
Reland "[NVPTX] Validate user-specified PTX version against SM version" (#180116)
2026-02-10 18:11:54 +00:00
rcp-opt.ll
…
read-global-variable-constant.ll
…
reduction-intrinsics.ll
…
redux-sync-f32.ll
[LLVM][NVPTX] Enable family specific support for a few intrinsics (#173268)
2026-01-08 06:34:29 +05:30
redux-sync.ll
…
refl1.ll
…
reg-copy.ll
…
reg-types.ll
…
reserved-smem-offset.ll
[NVPTX] Support intrinsics for reserved shared memory special registers (#182354)
2026-02-26 14:34:59 -08:00
rotate_64.ll
…
rotate-add.ll
…
rotate.ll
…
rsqrt-opt.ll
IR: Promote "denormal-fp-math" to a first class attribute (#174293)
2026-02-05 13:31:26 +00:00
rsqrt.ll
Reland "[NVPTX] Validate user-specified PTX version against SM version" (#180116)
2026-02-10 18:11:54 +00:00
sad-intrins.ll
…
scalar-to-vector.ll
Fix test from #175712 (#181905)
2026-02-17 13:39:36 -08:00
scalarize-non-coalescable-v2f32.ll
[NVPTX] Scalarize v2f32 instructions if input operand guarantees need for register coalescing (#180113)
2026-02-23 19:44:05 -08:00
sched1.ll
…
sched2.ll
…
setmaxnreg-sm100a.ll
[LLVM][NVPTX] Enable family specific support for a few intrinsics (#173268)
2026-01-08 06:34:29 +05:30
setmaxnreg.ll
…
sext-in-reg.ll
…
sext-params.ll
…
sext-setcc.ll
…
shfl-p.ll
…
shfl-sync-p.ll
…
shfl-sync.ll
…
shfl.ll
…
shift-opt.ll
[NVPTX][DagCombiner] Eliminate guards on shift amount because PTX shifts automatically clamp (#172431)
2025-12-17 12:13:36 -08:00
shift-parts.ll
…
short-ptr.ll
…
shuffle-vec-undef-init.ll
…
simple-call.ll
…
sm-version.ll
Reland "[NVPTX] Validate user-specified PTX version against SM version" (#180116)
2026-02-10 18:11:54 +00:00
speculative-execution-divergent-target.ll
…
sqrt-approx.ll
IR: Promote "denormal-fp-math" to a first class attribute (#174293)
2026-02-05 13:31:26 +00:00
st_bulk.ll
…
st-addrspace.ll
…
st-generic.ll
…
st-param-imm.ll
…
stackaddress.ll
[Clang] Add __builtin_stack_address (#148281)
2026-01-12 10:01:57 +01:00
stacksaverestore.ll
…
store-retval.ll
…
store-undef.ll
…
surf-read-cuda.ll
…
surf-read.ll
…
surf-tex.py
Reland "[NVPTX] Validate user-specified PTX version against SM version" (#180116)
2026-02-10 18:11:54 +00:00
surf-write-cuda.ll
…
surf-write.ll
…
switch-loop-header.mir
[MachineBasicBlock] Don't split loop header successor if the terminator is unanalyzable (#170146)
2025-12-03 15:55:59 +00:00
switch.ll
[NVPTX] Fixup and refactor brx.idx support (#171933)
2025-12-12 11:36:15 -08:00
symbol-naming.ll
…
szext.ll
…
tag-invariant-loads.ll
…
TailDuplication-convergent.ll
…
tanhf.ll
…
tcgen05-alloc.ll
…
tcgen05-commit.ll
…
tcgen05-cp.ll
…
tcgen05-fence.ll
…
tcgen05-ld-red.ll
[LLVM][NVPTX] Add support for tcgen05.ld.red Instruction (#175919)
2026-01-19 14:36:55 +05:30
tcgen05-ld.ll
…
tcgen05-mma-block-scale-invalid.ll
…
tcgen05-mma-block-scale-ptx88-aa.ll
[LLVM][NVPTX] Enable family specific support for a few intrinsics (#173268)
2026-01-08 06:34:29 +05:30
tcgen05-mma-block-scale-ptx88.ll
[LLVM][NVPTX] Enable family specific support for a few intrinsics (#173268)
2026-01-08 06:34:29 +05:30
tcgen05-mma-block-scale.ll
…
tcgen05-mma-disable-output-lane-i8.ll
[LLVM][NVPTX] Enable family specific support for a few intrinsics (#173268)
2026-01-08 06:34:29 +05:30
tcgen05-mma-disable-output-lane.ll
[LLVM][NVPTX] Enable family specific support for a few intrinsics (#173268)
2026-01-08 06:34:29 +05:30
tcgen05-mma-i8.ll
[NFC][NVPTX] Fix tcgen05.mma PTX instruction encoding (#186602)
2026-03-17 12:56:11 +01:00
tcgen05-mma-invalid.ll
…
tcgen05-mma-scale-d-invalid.ll
…
tcgen05-mma-scale-d.ll
[NFC][NVPTX] Fix tcgen05.mma PTX instruction encoding (#186602)
2026-03-17 12:56:11 +01:00
tcgen05-mma-tensor-formatted.ll
[LLVM-Tablegen] Pretty Printing Arguments in LLVM Intrinsics (#162629)
2025-11-17 09:00:40 -08:00
tcgen05-mma-ws-i8.ll
[LLVM][NVPTX] Enable family specific support for a few intrinsics (#173268)
2026-01-08 06:34:29 +05:30
tcgen05-mma-ws.ll
[LLVM][NVPTX] Enable family specific support for a few intrinsics (#173268)
2026-01-08 06:34:29 +05:30
tcgen05-mma.ll
[NFC][NVPTX] Fix tcgen05.mma PTX instruction encoding (#186602)
2026-03-17 12:56:11 +01:00
tcgen05-shift.ll
…
tcgen05-st.ll
…
tensormap_replace_invalid.ll
[NVPTX] Add intrinsics and codegen for tensormap.replace (#172458)
2026-01-01 11:19:26 +05:30
tensormap_replace_sm_100a.ll
[NVPTX] Add missing preconditions to tensormap replace tests (#174190)
2026-01-02 16:34:06 +05:30
tensormap_replace_sm_103a.ll
[NVPTX] Add proper precondition in tensormap_replace_sm_103a test (#174144)
2026-01-01 12:30:01 -05:00
tensormap_replace.ll
[NVPTX] Print param space sub-qualifiers where supported (#187350)
2026-03-20 20:44:56 -07:00
tex-read-cuda.ll
…
tex-read.ll
…
texsurf-queries.ll
…
thread-fence.ll
[NVPTX] Add a few more missing fence intrinsics (#166352)
2025-11-19 06:50:54 +05:30
tid-range.ll
…
trunc-setcc.ll
…
trunc-tofp.ll
…
unaligned-param-load-store.ll
…
unfold-masked-merge-vector-variablemask.ll
…
unreachable.ll
…
unrecognized-sm1x.ll
…
upgrade-nvvm-annotations.ll
…
used-bytes-mask.ll
[NVPTX] Print param space sub-qualifiers where supported (#187350)
2026-03-20 20:44:56 -07:00
vaargs.ll
…
variadics-backend.ll
…
variadics-lowering.ll
…
vec8.ll
…
vec-param-load.ll
…
vector-args.ll
…
vector-call.ll
…
vector-compare.ll
…
vector-global.ll
…
vector-loads.ll
…
vector-returns.ll
…
vector-select.ll
…
vector-stores.ll
…
vectorize-misaligned.ll
…
vote.ll
…
weak-global.ll
…
weak-linkage.ll
…
wgmma-sm90a-fence.ll
…
wmma-ptx60-sm70.py
…
wmma-ptx61-sm70.py
…
wmma-ptx63-sm72.py
…
wmma-ptx63-sm75.py
…
wmma-ptx64-sm70.py
…
wmma-ptx65-sm75.py
…
wmma-ptx71-sm80.py
…
wmma-ptx78-sm90.py
[LLVM][NVPTX] Enable family specific support for a few intrinsics (#173268)
2026-01-08 06:34:29 +05:30
wmma-ptx86-sm100a.py
[LLVM][NVPTX] Enable family specific support for a few intrinsics (#173268)
2026-01-08 06:34:29 +05:30
wmma-ptx86-sm101a.py
[LLVM][NVPTX] Enable family specific support for a few intrinsics (#173268)
2026-01-08 06:34:29 +05:30
wmma-ptx87-sm120a.py
[LLVM][NVPTX] Enable family specific support for a few intrinsics (#173268)
2026-01-08 06:34:29 +05:30
wmma-ptx88-sm100f.py
[LLVM][NVPTX] Enable family specific support for a few intrinsics (#173268)
2026-01-08 06:34:29 +05:30
wmma-ptx88-sm120a.py
[LLVM][NVPTX] Enable family specific support for a few intrinsics (#173268)
2026-01-08 06:34:29 +05:30
wmma-ptx88-sm120f.py
[LLVM][NVPTX] Enable family specific support for a few intrinsics (#173268)
2026-01-08 06:34:29 +05:30
wmma-ptx90-sm110f.py
[LLVM][NVPTX] Enable family specific support for a few intrinsics (#173268)
2026-01-08 06:34:29 +05:30
wmma-ptx91-sm120a.py
[MLIR][NVVM][NVPTX] Support for new mma/mma.sp variants from PTX 9.1 (#182325)
2026-02-24 16:40:22 +01:00
wmma-ptx91-sm120f.py
[MLIR][NVVM][NVPTX] Support for new mma/mma.sp variants from PTX 9.1 (#182325)
2026-02-24 16:40:22 +01:00
wmma.py
[MLIR][NVVM][NVPTX] Support for new mma/mma.sp variants from PTX 9.1 (#182325)
2026-02-24 16:40:22 +01:00
zeroext-32bit.ll
…