9050794e06
The original support for copyables leads to a regression in x264 in RISCV, this patch improves detection of the copyable candidates by more precise checking of the profitability and adds and extra check for splitnode reduction, if it is profitable. Fixes #184313 Reviewers: hiraditya, RKSimon Pull Request: https://github.com/llvm/llvm-project/pull/185697
71 lines
3.8 KiB
LLVM
71 lines
3.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt -O3 -S < %s | FileCheck %s
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; RUN: opt -passes="default<O3>" -S < %s | FileCheck %s
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target triple = "x86_64--"
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target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
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; PR42174 - https://bugs.llvm.org/show_bug.cgi?id=42174
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; This test should match the IR produced by clang after running -mem2reg.
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; All math before the final 'add' should be scalarized.
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define <4 x i32> @square(<4 x i32> %num, i32 %y, i32 %x, i32 %h, i32 %k, i32 %w, i32 %p, i32 %j, i32 %u) {
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; CHECK-LABEL: @square(
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; CHECK-NEXT: [[DIV:%.*]] = sdiv i32 [[K:%.*]], 2
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; CHECK-NEXT: [[MUL:%.*]] = mul nsw i32 [[P:%.*]], 6234
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; CHECK-NEXT: [[MUL5:%.*]] = mul nsw i32 [[H:%.*]], 75
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; CHECK-NEXT: [[DIV9:%.*]] = sdiv i32 [[J:%.*]], 3452
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; CHECK-NEXT: [[MUL13:%.*]] = mul nsw i32 [[W:%.*]], 53
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; CHECK-NEXT: [[DIV17:%.*]] = sdiv i32 [[X:%.*]], 820
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; CHECK-NEXT: [[MUL21:%.*]] = shl nsw i32 [[U:%.*]], 2
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; CHECK-NEXT: [[OP_RDX:%.*]] = add nsw i32 [[DIV17]], 317426
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; CHECK-NEXT: [[OP_RDX9:%.*]] = add nsw i32 [[DIV]], [[DIV9]]
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; CHECK-NEXT: [[OP_RDX10:%.*]] = add i32 [[MUL5]], [[MUL13]]
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; CHECK-NEXT: [[OP_RDX11:%.*]] = add i32 [[MUL]], [[MUL21]]
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; CHECK-NEXT: [[OP_RDX12:%.*]] = add i32 [[OP_RDX]], [[OP_RDX9]]
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; CHECK-NEXT: [[OP_RDX13:%.*]] = add i32 [[OP_RDX10]], [[OP_RDX11]]
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; CHECK-NEXT: [[OP_RDX14:%.*]] = add i32 [[OP_RDX12]], [[OP_RDX13]]
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; CHECK-NEXT: [[OP_RDX15:%.*]] = add i32 [[OP_RDX14]], [[Y:%.*]]
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; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i32> poison, i32 [[OP_RDX15]], i64 0
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; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> poison, <4 x i32> zeroinitializer
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; CHECK-NEXT: [[ADD29:%.*]] = add <4 x i32> [[TMP2]], [[NUM:%.*]]
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; CHECK-NEXT: ret <4 x i32> [[ADD29]]
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;
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%add = add <4 x i32> %num, <i32 1, i32 1, i32 1, i32 1>
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%div = sdiv i32 %k, 2
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%splatinsert = insertelement <4 x i32> undef, i32 %div, i32 0
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%splat = shufflevector <4 x i32> %splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer
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%add1 = add <4 x i32> %add, %splat
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%mul = mul nsw i32 %p, 6234
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%splatinsert2 = insertelement <4 x i32> undef, i32 %mul, i32 0
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%splat3 = shufflevector <4 x i32> %splatinsert2, <4 x i32> undef, <4 x i32> zeroinitializer
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%add4 = add <4 x i32> %add1, %splat3
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%mul5 = mul nsw i32 75, %h
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%splatinsert6 = insertelement <4 x i32> undef, i32 %mul5, i32 0
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%splat7 = shufflevector <4 x i32> %splatinsert6, <4 x i32> undef, <4 x i32> zeroinitializer
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%add8 = add <4 x i32> %add4, %splat7
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%div9 = sdiv i32 %j, 3452
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%splatinsert10 = insertelement <4 x i32> undef, i32 %div9, i32 0
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%splat11 = shufflevector <4 x i32> %splatinsert10, <4 x i32> undef, <4 x i32> zeroinitializer
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%add12 = add <4 x i32> %add8, %splat11
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%mul13 = mul nsw i32 53, %w
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%splatinsert14 = insertelement <4 x i32> undef, i32 %mul13, i32 0
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%splat15 = shufflevector <4 x i32> %splatinsert14, <4 x i32> undef, <4 x i32> zeroinitializer
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%add16 = add <4 x i32> %add12, %splat15
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%div17 = sdiv i32 %x, 820
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%splatinsert18 = insertelement <4 x i32> undef, i32 %div17, i32 0
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%splat19 = shufflevector <4 x i32> %splatinsert18, <4 x i32> undef, <4 x i32> zeroinitializer
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%add20 = add <4 x i32> %add16, %splat19
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%mul21 = mul nsw i32 4, %u
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%splatinsert22 = insertelement <4 x i32> undef, i32 %mul21, i32 0
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%splat23 = shufflevector <4 x i32> %splatinsert22, <4 x i32> undef, <4 x i32> zeroinitializer
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%add24 = add <4 x i32> %add20, %splat23
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%splatinsert25 = insertelement <4 x i32> undef, i32 %y, i32 0
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%splat26 = shufflevector <4 x i32> %splatinsert25, <4 x i32> undef, <4 x i32> zeroinitializer
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%add27 = add <4 x i32> %add24, %splat26
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%add28 = add <4 x i32> %add27, <i32 25, i32 25, i32 25, i32 25>
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%add29 = add <4 x i32> %add28, <i32 317400, i32 317400, i32 317400, i32 317400>
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ret <4 x i32> %add29
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}
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