Matt Arsenault 9eefa922f8

AMDGPU/GlobalISel: Remove getVRegDef null checks in selector (#115530) ...

We should be able to assume every virtual register is defined.

2024-11-11 12:58:06 -08:00

..

AsmParser

[AMDGPU] Qualify auto. NFC. (#110878)

2024-10-03 13:07:54 +01:00

Disassembler

[AMDGPU] Qualify auto. NFC. (#110878)

2024-10-03 13:07:54 +01:00

MCA

[AMDGPU] Concatenate nested namespaces. NFC.

2024-07-16 15:36:49 +01:00

MCTargetDesc

[MC] Make generated MCInstPrinter::getMnemonic const (NFC) (#114682)

2024-11-03 20:37:26 +03:00

TargetInfo

[AMDGPU] Eliminate SIMCCodeEmitter and de-virtualise encoding methods.

2023-07-05 10:13:33 +01:00

Utils

[AMDGPU][True16][MC] VOP2 update instructions with fake16 format (#114436)

2024-11-05 16:12:49 -05:00

AMDGPU.h

[NewPM][AMDGPU] Port SIPreAllocateWWMRegs to NPM (#109939)

2024-10-22 15:37:08 +05:30

AMDGPU.td

[AMDGPU] Introduce a "new" target feature xf32-insts (#115214)

2024-11-07 12:41:06 -05:00

AMDGPUAliasAnalysis.cpp

[AA] Skip the layer of indirection in returning conservative results.

2023-07-28 12:13:35 -07:00

AMDGPUAliasAnalysis.h

[IR] Don't include Module.h in Analysis.h (NFC) (#97023)

2024-06-28 14:30:47 +02:00

AMDGPUAlwaysInlinePass.cpp

[AMDGPU] Always Inline preserved analyses (#91198)

2024-05-09 06:17:01 -04:00

AMDGPUAnnotateKernelFeatures.cpp

…

AMDGPUAnnotateUniformValues.cpp

[AMDGPU] Move AMDGPUMemoryUtils out of Utils. NFC. (#104930)

2024-08-20 16:15:46 +01:00

AMDGPUArgumentUsageInfo.cpp

AMDGPU: Add plumbing for private segment size argument (#96445)

2024-06-25 16:20:51 +02:00

AMDGPUArgumentUsageInfo.h

[NFC][AMDGPU] Assert no bad shift operations will happen (#108416)

2024-09-24 14:47:57 +04:00

AMDGPUAsanInstrumentation.cpp

[AMDGPU] Qualify auto. NFC. (#110878)

2024-10-03 13:07:54 +01:00

AMDGPUAsanInstrumentation.h

[AMDGPU] Update instrumentAddress method to support aligned size and unusual size accesses. (#104804)

2024-08-21 10:31:42 +05:30

AMDGPUAsmPrinter.cpp

Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"

2024-11-08 20:21:16 -05:00

AMDGPUAsmPrinter.h

[AMDGPU] Convert AMDGPUResourceUsageAnalysis pass from Module to MF pass (#102913)

2024-09-30 11:43:34 +01:00

AMDGPUAtomicOptimizer.cpp

Fix typo "instrinsic" (#112899)

2024-10-18 15:58:33 +01:00

AMDGPUAttributes.def

…

AMDGPUAttributor.cpp

[NFC] clang-format -i llvm/lib/Target/AMDGPU/AMDGPUAttributor.cpp

2024-10-31 11:44:15 -04:00

AMDGPUCallingConv.td

[NFC][AMDGPU] Use !foreach to replace explicit list of registers (#114005)

2024-10-29 10:50:06 -04:00

AMDGPUCallLowering.cpp

Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"

2024-11-08 20:21:16 -05:00

AMDGPUCallLowering.h

[AMDGPU] ISel for @llvm.amdgcn.cs.chain intrinsic (#68186)

2023-11-06 12:30:07 +01:00

AMDGPUCodeGenPrepare.cpp

[LLVM] Make more use of IRBuilder::CreateIntrinsic. NFC. (#112706)

2024-10-17 16:20:43 +01:00

AMDGPUCombine.td

AMDGPU/GlobalISel: Run redundant_and combine in RegBankCombiner (#112353)

2024-10-16 09:43:16 +02:00

AMDGPUCombinerHelper.cpp

AMDGPU/GlobalISel: Use correct type for intrinsic ID

2024-05-30 14:31:19 +02:00

AMDGPUCombinerHelper.h

[NFC] Eliminate top-level "using namespace" from some headers. (#102751)

2024-08-11 13:10:48 -07:00

AMDGPUCtorDtorLowering.cpp

AMDGPU: Add instruction flags when lowering ctor/dtor (#111652)

2024-10-09 18:03:35 +04:00

AMDGPUCtorDtorLowering.h

…

AMDGPUExportClustering.cpp

…

AMDGPUExportClustering.h

…

AMDGPUFeatures.td

[AMDGPU] Rename LocalMemorySize features to AddressableLocalMemorySize (#110242)

2024-09-30 10:29:31 +01:00

AMDGPUFrameLowering.cpp

…

AMDGPUFrameLowering.h

…

AMDGPUGenRegisterBankInfo.def

Silence illegal address computation warning (#83244)

2024-03-01 21:41:12 +05:30

AMDGPUGISel.td

AMDGPU/GlobalISel: Handle atomic sextload and zextload (#111721)

2024-10-31 07:44:52 -07:00

AMDGPUGlobalISelDivergenceLowering.cpp

[CodeGen][NewPM] Split MachinePostDominators into a concrete analysis result (#95113)

2024-06-12 14:29:22 +08:00

AMDGPUGlobalISelUtils.cpp

[AMDGPU] Remove hasAtomicFaddRtnForTy as it is not used anywhere (#82841)

2024-02-23 21:14:38 -05:00

AMDGPUGlobalISelUtils.h

[AMDGPU] Remove hasAtomicFaddRtnForTy as it is not used anywhere (#82841)

2024-02-23 21:14:38 -05:00

AMDGPUHSAMetadataStreamer.cpp

AMDGPU: Treat uint32_max as the default value for amdgpu-max-num-workgroups (#113751)

2024-11-05 12:50:44 -08:00

AMDGPUHSAMetadataStreamer.h

[AMDGPU] MCExpr-ify AMDGPU HSAMetadata (#94788)

2024-06-26 16:39:08 +01:00

AMDGPUIGroupLP.cpp

[llvm] Remove redundant calls to std::unique_ptr<T>::get (NFC) (#113415)

2024-10-23 10:44:09 -07:00

AMDGPUIGroupLP.h

[AMDGPU] Do not attempt to fallback to default mutations (#83208)

2024-02-27 18:04:59 -08:00

AMDGPUImageIntrinsicOptimizer.cpp

[LLVM] Make more use of IRBuilder::CreateIntrinsic. NFC. (#112706)

2024-10-17 16:20:43 +01:00

AMDGPUInsertDelayAlu.cpp

[AMDGPU] Use the SchedModel available in SIInstrInfo (#110859)

2024-10-02 18:17:27 +02:00

AMDGPUInstCombineIntrinsic.cpp

[LLVM] Make more use of IRBuilder::CreateIntrinsic. NFC. (#112706)

2024-10-17 16:20:43 +01:00

AMDGPUInstrInfo.cpp

Restore "[GlobalISel] GIntrinsic subclass to represent intrinsics in Generic Machine IR"

2023-07-27 14:49:17 +05:30

AMDGPUInstrInfo.h

AMDGPU/GlobalISel: Use correct type for intrinsic ID

2024-05-30 14:31:19 +02:00

AMDGPUInstrInfo.td

[AMDGPU] Add a trap lowering workaround for gfx11 (#85854)

2024-04-24 09:43:54 -04:00

AMDGPUInstructions.td

AMDGPU/GlobalISel: Handle atomic sextload and zextload (#111721)

2024-10-31 07:44:52 -07:00

AMDGPUInstructionSelector.cpp

AMDGPU/GlobalISel: Remove getVRegDef null checks in selector (#115530)

2024-11-11 12:58:06 -08:00

AMDGPUInstructionSelector.h

[AMDGPU] modify named barrier builtins and intrinsics (#114550)

2024-11-06 10:37:22 -08:00

AMDGPUISelDAGToDAG.cpp

AMDGPU: Don't avoid clamp of bit shift in BFE pattern (#115372)

2024-11-07 14:15:33 -08:00

AMDGPUISelDAGToDAG.h

AMDGPU: Don't avoid clamp of bit shift in BFE pattern (#115372)

2024-11-07 14:15:33 -08:00

AMDGPUISelLowering.cpp

[AMDGPU] Remove unused AMDGPUISD enum members (NFC) (#115582)

2024-11-11 23:39:20 +03:00

AMDGPUISelLowering.h

[AMDGPU] Remove unused AMDGPUISD enum members (NFC) (#115582)

2024-11-11 23:39:20 +03:00

AMDGPULateCodeGenPrepare.cpp

[AMDGPU] Avoid repeated hash lookups (NFC) (#113409)

2024-10-22 23:02:34 -07:00

AMDGPULegalizerInfo.cpp

[AMDGPU] modify named barrier builtins and intrinsics (#114550)

2024-11-06 10:37:22 -08:00

AMDGPULegalizerInfo.h

Reapply "[AMDGPU][GlobalISel] Fix load/store of pointer vectors, buffer.*.pN (#110714)" v3 (#114443)

2024-11-01 11:13:29 -05:00

AMDGPULibCalls.cpp

[SimplifyLibCall][Attribute] Fix bug where we may keep range attr with incompatible type (#112649)

2024-10-17 10:32:55 -05:00

AMDGPULibFunc.cpp

[llvm][AMDGPU] Avoid Type::getPointerTo() (NFC)

2024-09-30 20:15:50 -05:00

AMDGPULibFunc.h

AMDGPU: Use pown instead of pow if known integral

2023-09-01 08:22:16 -04:00

AMDGPULowerBufferFatPointers.cpp

[AMDGPU] Support nuw and nusw in buffer fat pointer lowering (#115039)

2024-11-06 11:42:47 -06:00

AMDGPULowerKernelArguments.cpp

[LLVM] Add Intrinsic::getDeclarationIfExists (#112428)

2024-10-16 07:21:10 -07:00

AMDGPULowerKernelAttributes.cpp

[LLVM] Add Intrinsic::getDeclarationIfExists (#112428)

2024-10-16 07:21:10 -07:00

AMDGPULowerModuleLDSPass.cpp

[AMDGPU] Fix a warning

2024-11-06 12:08:27 -08:00

AMDGPUMachineFunction.cpp

Remove unused variable to fix '[AMDGPU] modify named barrier builtins and intrinsics (#114550)'

2024-11-06 20:49:39 +00:00

AMDGPUMachineFunction.h

Reland "[amdgpu] Add llvm.amdgcn.init.whole.wave intrinsic" (#108512)

2024-09-13 11:54:30 +02:00

AMDGPUMachineModuleInfo.cpp

[IR] Don't include Module.h in Analysis.h (NFC) (#97023)

2024-06-28 14:30:47 +02:00

AMDGPUMachineModuleInfo.h

[IR] Remove Function.h include from Analysis.h (NFC) (#97056)

2024-06-28 16:41:00 +02:00

AMDGPUMacroFusion.cpp

[DAG] clang-format createBranchMacroFusionDAGMutation calls. NFC.

2023-11-20 12:13:09 +00:00

AMDGPUMacroFusion.h

…

AMDGPUMarkLastScratchLoad.cpp

[CodeGen][NewPM] Port LiveIntervals to new pass manager (#98118)

2024-07-10 19:34:48 +08:00

AMDGPUMCInstLower.cpp

[llvm] Don't call raw_string_ostream::flush() (NFC)

2024-09-20 12:19:59 -05:00

AMDGPUMCInstLower.h

[AMDGPU] Qualify auto. NFC. (#110878)

2024-10-03 13:07:54 +01:00

AMDGPUMCResourceInfo.cpp

[AMDGPU] Fix resource usage information for unnamed functions (#115320)

2024-11-07 18:24:54 +00:00

AMDGPUMCResourceInfo.h

Add and call AMDGPUMCResourceInfo::reset method (#110818)

2024-10-02 14:17:01 +02:00

AMDGPUMemoryUtils.cpp

[AMDGPU] modify named barrier builtins and intrinsics (#114550)

2024-11-06 10:37:22 -08:00

AMDGPUMemoryUtils.h

[AMDGPU] modify named barrier builtins and intrinsics (#114550)

2024-11-06 10:37:22 -08:00

AMDGPUMIRFormatter.cpp

[AMDGPU] Introduce a pseudo mnemonic for S_DELAY_ALU in MIR. (#96004)

2024-06-20 15:59:08 -04:00

AMDGPUMIRFormatter.h

[AMDGPU] Introduce a pseudo mnemonic for S_DELAY_ALU in MIR. (#96004)

2024-06-20 15:59:08 -04:00

AMDGPUOpenCLEnqueuedBlockLowering.cpp

[NFC] Remove Type::getInt8PtrTy (#71029)

2023-11-07 17:26:26 +01:00

AMDGPUPassRegistry.def

[NewPM][AMDGPU] Port SIPreAllocateWWMRegs to NPM (#109939)

2024-10-22 15:37:08 +05:30

AMDGPUPerfHintAnalysis.cpp

[AMDGPU] Qualify auto. NFC. (#110878)

2024-10-03 13:07:54 +01:00

AMDGPUPerfHintAnalysis.h

NewPM/AMDGPU: Port AMDGPUPerfHintAnalysis to new pass manager (#102645)

2024-08-11 15:11:10 +04:00

AMDGPUPostLegalizerCombiner.cpp

[AMDGPU][GlobalISel] Disable fixed-point iteration in all Combiners (#105517)

2024-08-22 17:14:53 +01:00

AMDGPUPredicateControl.td

[AMDGPU][TableGen][NFC] Combine predicates without using classes. (#82346)

2024-02-21 11:45:36 +00:00

AMDGPUPreLegalizerCombiner.cpp

[AMDGPU][GlobalISel] Disable fixed-point iteration in all Combiners (#105517)

2024-08-22 17:14:53 +01:00

AMDGPUPrintfRuntimeBinding.cpp

[AMDGPU] Qualify auto. NFC. (#110878)

2024-10-03 13:07:54 +01:00

AMDGPUPromoteAlloca.cpp

AMDGPU: Improve vector of pointer handling in amdgpu-promote-alloca (#114144)

2024-11-06 08:47:15 -08:00

AMDGPUPromoteKernelArguments.cpp

[AMDGPU] Move AMDGPUMemoryUtils out of Utils. NFC. (#104930)

2024-08-20 16:15:46 +01:00

AMDGPUPTNote.h

…

AMDGPURegBankCombiner.cpp

[AMDGPU][GlobalISel] Disable fixed-point iteration in all Combiners (#105517)

2024-08-22 17:14:53 +01:00

AMDGPURegBankSelect.cpp

Revert "[CodeGen] Remove applySplitCriticalEdges in MachineDominatorTree (#97055)"

2024-07-11 09:13:37 +02:00

AMDGPURegBankSelect.h

AMDGPU/GlobalISel: Add stub custom regbankselect pass

2023-01-30 16:18:20 -04:00

AMDGPURegisterBankInfo.cpp

[AMDGPU] modify named barrier builtins and intrinsics (#114550)

2024-11-06 10:37:22 -08:00

AMDGPURegisterBankInfo.h

[AMDGPU] Make isScalarLoadLegal a member of AMDGPURegisterBankInfo. NFC.

2024-01-09 11:53:12 +00:00

AMDGPURegisterBanks.td

[AMDGPU][True16] Don't use the VGPR_LO/HI16 register classes. (#76440)

2023-12-28 11:48:25 +00:00

AMDGPURemoveIncompatibleFunctions.cpp

[AMDGPU] Fix and add namespace closing comments. NFC.

2024-07-16 16:56:31 +01:00

AMDGPUReserveWWMRegs.cpp

[AMDGPU] Split vgpr regalloc pipeline (#93526)

2024-09-30 19:55:42 +05:30

AMDGPUResourceUsageAnalysis.cpp

[AMDGPU] Factor out getNumUsedPhysRegs(). NFC. (#112624)

2024-10-17 00:47:19 -07:00

AMDGPUResourceUsageAnalysis.h

[AMDGPU] Convert AMDGPUResourceUsageAnalysis pass from Module to MF pass (#102913)

2024-09-30 11:43:34 +01:00

AMDGPURewriteOutArguments.cpp

[llvm] Stop including llvm/ADT/SmallSet.h (NFC)

2023-11-11 12:32:15 -08:00

AMDGPURewriteUndefForPHI.cpp

[AMDGPU] Do not preserve UniformityInfo (#76696)

2024-01-02 13:42:56 +05:30

AMDGPUSearchableTables.td

AMDGPU: Remove flat/global fmin/fmax intrinsics (#105642)

2024-10-09 09:27:28 +04:00

AMDGPUSetWavePriority.cpp

…

AMDGPUSplitModule.cpp

(reland) [AMDGPU][SplitModule] Handle !callees metadata (#108802)

2024-10-15 07:16:57 +02:00

AMDGPUSplitModule.h

[NFC][AMDGPU] Make AMDGPUSplitModule a ModulePass (#95773)

2024-06-18 09:16:32 +02:00

AMDGPUSubtarget.cpp

AMDGPU: Treat uint32_max as the default value for amdgpu-max-num-workgroups (#113751)

2024-11-05 12:50:44 -08:00

AMDGPUSubtarget.h

[AMDGPU] Rename LocalMemorySize features to AddressableLocalMemorySize (#110242)

2024-09-30 10:29:31 +01:00

AMDGPUSwLowerLDS.cpp

[LLVM] Make more use of IRBuilder::CreateIntrinsic. NFC. (#112706)

2024-10-17 16:20:43 +01:00

AMDGPUTargetMachine.cpp

[AMDGPU][MIR] Serialize SpillPhysVGPRs (#113129)

2024-11-05 13:17:25 +05:30

AMDGPUTargetMachine.h

[AMDGPU][NewPM] Fill out addILPOpts. (#108514)

2024-10-16 13:30:46 +05:30

AMDGPUTargetObjectFile.cpp

[llvm] Use StringRef::{starts,ends}_with (NFC) (#74956)

2023-12-11 21:01:36 -08:00

AMDGPUTargetObjectFile.h

…

AMDGPUTargetTransformInfo.cpp

[AMDGPU] Use wider loop lowering type for LowerMemIntrinsics (#112332)

2024-10-28 09:04:19 +01:00

AMDGPUTargetTransformInfo.h

[AMDGPU] Allow casts between the Global and Constant Addr Spaces in isValidAddrSpaceCast (#112493)

2024-10-22 09:33:21 +02:00

AMDGPUUnifyDivergentExitNodes.cpp

[NFC] Rename Intrinsic::getDeclaration to getOrInsertDeclaration (#111752)

2024-10-11 05:26:03 -07:00

AMDGPUUnifyDivergentExitNodes.h

[llvm] Fix include guards

2023-06-13 10:47:18 +01:00

AMDGPUUnifyMetadata.cpp

[AMDGPU] Qualify auto. NFC. (#110878)

2024-10-03 13:07:54 +01:00

AMDKernelCodeT.h

…

BUFInstructions.td

[AMDGPU] Simplify GFX12 VBUFFER definitions. NFC. (#114403)

2024-11-01 10:06:45 +00:00

CaymanInstructions.td

…

CMakeLists.txt

[AMDGPU] Split vgpr regalloc pipeline (#93526)

2024-09-30 19:55:42 +05:30

DSDIRInstructions.td

AMDGPU: Use PseudoInstr to name SIMCInstr for DSDIR and SOPs, NFC (#87537)

2024-04-03 11:35:09 -07:00

DSInstructions.td

AMDGPU/GlobalISel: Handle atomic sextload and zextload (#111721)

2024-10-31 07:44:52 -07:00

EvergreenInstructions.td

DAG: Replace bitwidth with type in suffix in atomic tablegen ops (#94845)

2024-06-13 11:52:22 +02:00

EXPInstructions.td

[AMDGPU] Remove unnecessary predicates from aliases. NFC. (#91602)

2024-05-10 15:04:38 +01:00

FLATInstructions.td

AMDGPU/GlobalISel: Handle atomic sextload and zextload (#111721)

2024-10-31 07:44:52 -07:00

GCNCreateVOPD.cpp

[AMDGPU] clang-tidy: define trivial constructors with = default. NFC.

2024-07-16 15:41:54 +01:00

GCNDPPCombine.cpp

[AMDGPU] Qualify auto. NFC. (#110878)

2024-10-03 13:07:54 +01:00

GCNDPPCombine.h

[CodeGen][NewPM] Make MFProperties methods const NFC (#113304)

2024-10-25 00:24:44 +05:30

GCNHazardRecognizer.cpp

[AMDGPU] Use the SchedModel available in SIInstrInfo (#110859)

2024-10-02 18:17:27 +02:00

GCNHazardRecognizer.h

[AMDGPU] Use the SchedModel available in SIInstrInfo (#110859)

2024-10-02 18:17:27 +02:00

GCNILPSched.cpp

[AMDGPU] Qualify auto. NFC. (#110878)

2024-10-03 13:07:54 +01:00

GCNIterativeScheduler.cpp

[AMDGPU] Optionally Use GCNRPTrackers during scheduling (#93090)

2024-10-09 09:54:11 -07:00

GCNIterativeScheduler.h

…

GCNMinRegStrategy.cpp

[AMDGPU] Qualify auto. NFC. (#110878)

2024-10-03 13:07:54 +01:00

GCNNSAReassign.cpp

[NewPM][CodeGen] Port LiveRegMatrix to NPM (#109938)

2024-10-22 15:28:04 +05:30

GCNPreRALongBranchReg.cpp

[AMDGPU] Reserve SGPR pair when long branches are present

2023-06-29 16:50:46 -05:00

GCNPreRAOptimizations.cpp

[AMDGPU] Use Lo_32 and Hi_32 helpers (NFC) (#109413)

2024-09-20 14:35:38 +02:00

GCNProcessors.td

[AMDGPU] Add a new target for gfx1153 (#113138)

2024-10-23 12:56:58 +09:00

GCNRegPressure.cpp

[AMDGPU] Optionally Use GCNRPTrackers during scheduling (#93090)

2024-10-09 09:54:11 -07:00

GCNRegPressure.h

[AMDGPU] Optionally Use GCNRPTrackers during scheduling (#93090)

2024-10-09 09:54:11 -07:00

GCNRewritePartialRegUses.cpp

LiveInterval: Make verify functions return bool (#109672)

2024-09-24 08:32:47 +04:00

GCNSchedStrategy.cpp

[AMDGPU] Fix expensive check

2024-10-09 10:24:06 -07:00

GCNSchedStrategy.h

[AMDGPU] Optionally Use GCNRPTrackers during scheduling (#93090)

2024-10-09 09:54:11 -07:00

GCNSubtarget.cpp

[AMDGPU] Rename LocalMemorySize features to AddressableLocalMemorySize (#110242)

2024-09-30 10:29:31 +01:00

GCNSubtarget.h

[AMDGPU] Introduce a "new" target feature xf32-insts (#115214)

2024-11-07 12:41:06 -05:00

GCNVOPDUtils.cpp

[AMDGPU] Update VOP instructions for GFX12 (#74853)

2023-12-12 11:38:24 +01:00

GCNVOPDUtils.h

…

InstCombineTables.td

[TableGen] Eliminate static CodeGenIntrinsicMap in PatternParser (#107339)

2024-09-07 15:11:34 -07:00

MIMGInstructions.td

[AMDGPU][MC] Fix disassemble of image_gather4 with d16 (#114609)

2024-11-05 10:36:54 -08:00

R600.h

[NFC][CodeGen] Change CodeGenOpt::Level/CodeGenFileType into enum classes (#66295)

2023-09-14 14:10:14 -07:00

R600.td

[AMDGPU][NFC] Extend PredicateControl to support True16 predicates. (#82245)

2024-02-20 11:37:44 +00:00

R600AsmPrinter.cpp

…

R600AsmPrinter.h

…

R600ClauseMergePass.cpp

…

R600ControlFlowFinalizer.cpp

[AMDGPU] clang-tidy: no else after return etc. NFC. (#99298)

2024-07-17 21:11:00 +01:00

R600Defines.h

…

R600EmitClauseMarkers.cpp

[AMDGPU] Use range-based for loops (NFC) (#106184)

2024-08-27 06:46:01 -07:00

R600ExpandSpecialInstrs.cpp

…

R600FrameLowering.cpp

…

R600FrameLowering.h

[llvm] Consistently respect naked fn attribute in TargetFrameLowering::hasFP() (#106014)

2024-10-18 09:35:42 +04:00

R600InstrFormats.td

…

R600InstrInfo.cpp

[AMDGPU] Use range-based for loops (NFC) (#106328)

2024-08-28 01:13:33 -07:00

R600InstrInfo.h

[TII][RISCV] Add renamable bit to copyPhysReg (#91179)

2024-08-27 10:08:43 +08:00

R600InstrInfo.td

…

R600Instructions.td

[AMDGPU] Generic lowering for rint and nearbyint (#69596)

2023-11-14 18:49:21 +01:00

R600ISelDAGToDAG.cpp

[NFC] Eliminate top-level "using namespace" from some headers. (#102751)

2024-08-11 13:10:48 -07:00

R600ISelLowering.cpp

[AMDGPU] Avoid repeated hash lookups (NFC) (#111787)

2024-10-10 08:18:28 -07:00

R600ISelLowering.h

…

R600MachineCFGStructurizer.cpp

[AMDGPU] clang-tidy: no else after return etc. NFC. (#99298)

2024-07-17 21:11:00 +01:00

R600MachineFunctionInfo.cpp

…

R600MachineFunctionInfo.h

…

R600MachineScheduler.cpp

[AMDGPU] Use range-based for loops (NFC) (#106184)

2024-08-27 06:46:01 -07:00

R600MachineScheduler.h

[NFC] Eliminate top-level "using namespace" from some headers. (#102751)

2024-08-11 13:10:48 -07:00

R600MCInstLower.cpp

…

R600OpenCLImageTypeLoweringPass.cpp

[AMDGPU] Qualify auto. NFC. (#110878)

2024-10-03 13:07:54 +01:00

R600OptimizeVectorRegisters.cpp

[AMDGPU] clang-tidy: use emplace_back instead of push_back. NFC.

2024-07-17 08:27:35 +01:00

R600Packetizer.cpp

[Target] Use range-based for loops (NFC) (#98705)

2024-07-13 17:40:51 -07:00

R600Processors.td

[AMDGPU] Rename LocalMemorySize features to AddressableLocalMemorySize (#110242)

2024-09-30 10:29:31 +01:00

R600RegisterInfo.cpp

…

R600RegisterInfo.h

…

R600RegisterInfo.td

…

R600Schedule.td

…

R600Subtarget.cpp

[AMDGPU] Rename LocalMemorySize features to AddressableLocalMemorySize (#110242)

2024-09-30 10:29:31 +01:00

R600Subtarget.h

[InitUndef] Enable the InitUndef pass on non-AMDGPU targets (#108353)

2024-09-16 09:48:25 +02:00

R600TargetMachine.cpp

[AMDGPU][R600] Move R600CodeGenPassBuilder into R600TargetMachine(NFC). (#103721)

2024-08-19 20:40:12 +05:30

R600TargetMachine.h

[AMDGPU][R600] Move R600CodeGenPassBuilder into R600TargetMachine(NFC). (#103721)

2024-08-19 20:40:12 +05:30

R600TargetTransformInfo.cpp

[IR] Add getDataLayout() helpers to Function and GlobalValue (#96919)

2024-06-28 08:36:49 +02:00

R600TargetTransformInfo.h

[LV][NFC] Use ElementCount for getMaxInterleaveFactor

2023-02-22 10:15:05 +00:00

R700Instructions.td

…

SIAnnotateControlFlow.cpp

[NFC] Rename Intrinsic::getDeclaration to getOrInsertDeclaration (#111752)

2024-10-11 05:26:03 -07:00

SIDefines.h

[AMDGPU] modify named barrier builtins and intrinsics (#114550)

2024-11-06 10:37:22 -08:00

SIFixSGPRCopies.cpp

[AMDGPU] Qualify auto. NFC. (#110878)

2024-10-03 13:07:54 +01:00

SIFixSGPRCopies.h

AMDGPU/NewPM: Port SIFixSGPRCopies to new pass manager (#102614)

2024-08-09 17:52:41 +04:00

SIFixVGPRCopies.cpp

AMDGPU: Make SIFixVGPRCopies preserve everything

2023-07-06 10:26:21 -04:00

SIFoldOperands.cpp

AMDGPU: Fold more scalar operations on frame index to VALU (#115059)

2024-11-07 19:02:20 -08:00

SIFoldOperands.h

AMDGPU/NewPM: Port SIFoldOperands to new pass manager (#105801)

2024-08-29 11:34:54 +05:30

SIFormMemoryClauses.cpp

[AMDGPU] Avoid repeated hash lookups (NFC) (#112115)

2024-10-12 22:07:22 -07:00

SIFrameLowering.cpp

[llvm] Consistently respect naked fn attribute in TargetFrameLowering::hasFP() (#106014)

2024-10-18 09:35:42 +04:00

SIFrameLowering.h

[llvm] Consistently respect naked fn attribute in TargetFrameLowering::hasFP() (#106014)

2024-10-18 09:35:42 +04:00

SIInsertHardClauses.cpp

[Codegen] Make Width in getMemOperandsWithOffsetWidth a LocationSize. (#83875)

2024-03-06 17:40:13 +00:00

SIInsertWaitcnts.cpp

[AMDGPU] Skip VGPR deallocation for waveslot limited kernels (#112765)

2024-10-21 09:39:52 -07:00

SIInstrFormats.td

[AMDGPU] Move renamedInGFX9 from TableGen to SIInstrInfo helper function/macro to free up a bit slot (#82787)

2024-09-25 20:38:51 -04:00

SIInstrInfo.cpp

[AMDGPU][True16][MC] VOP2 update instructions with fake16 format (#114436)

2024-11-05 16:12:49 -05:00

SIInstrInfo.h

[AMDGPU] modify named barrier builtins and intrinsics (#114550)

2024-11-06 10:37:22 -08:00

SIInstrInfo.td

[AMDGPU][True16][MC] VOP2 update instructions with fake16 format (#114436)

2024-11-05 16:12:49 -05:00

SIInstructions.td

AMDGPU: Default to selecting frame indexes to SGPRs (#115060)

2024-11-08 19:01:59 -08:00

SIISelLowering.cpp

Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"

2024-11-08 20:21:16 -05:00

SIISelLowering.h

AMDGPU: Custom expand flat cmpxchg which may access private (#109410)

2024-11-04 09:29:38 -08:00

SILateBranchLowering.cpp

[AMDGPU] Qualify auto. NFC. (#110878)

2024-10-03 13:07:54 +01:00

SILoadStoreOptimizer.cpp

[AMDGPU] Qualify auto. NFC. (#110878)

2024-10-03 13:07:54 +01:00

SILoadStoreOptimizer.h

[CodeGen][NewPM] Make MFProperties methods const NFC (#113304)

2024-10-25 00:24:44 +05:30

SILowerControlFlow.cpp

[AMDGPU][NFC] Correct description (#112847)

2024-10-18 10:41:16 +02:00

SILowerI1Copies.cpp

AMDGPU/NewPM: Port SILowerI1Copies to new pass manager (#102663)

2024-08-10 07:08:22 +04:00

SILowerI1Copies.h

AMDGPU/GlobalISelDivergenceLowering: select divergent i1 phis (#80003)

2024-02-05 14:07:01 +01:00

SILowerSGPRSpills.cpp

[AMDGPU] Correct pass dependencies for SILowerSGPRSpills (#109937)

2024-10-22 15:20:54 +05:30

SILowerSGPRSpills.h

[CodeGen][NewPM] Make MFProperties methods const NFC (#113304)

2024-10-25 00:24:44 +05:30

SILowerWWMCopies.cpp

[NewPM][CodeGen] Port VirtRegMap to NPM (#109936)

2024-10-22 15:15:56 +05:30

SIMachineFunctionInfo.cpp

Revert "[AMDGPU][MIR] Serialize NumPhysicalVGPRSpillLanes" (#115353)

2024-11-07 13:02:51 -05:00

SIMachineFunctionInfo.h

Revert "[AMDGPU][MIR] Serialize NumPhysicalVGPRSpillLanes" (#115353)

2024-11-07 13:02:51 -05:00

SIMachineScheduler.cpp

[AMDGPU] Avoid repeated map lookups (NFC) (#112819)

2024-10-21 10:35:53 -07:00

SIMachineScheduler.h

[AMDGPU] Default-initialize uninitialized class member variables (#108428)

2024-09-24 14:48:21 +04:00

SIMemoryLegalizer.cpp

[AMDGPU] Only emit SCOPE_SYS global_wb (#110636)

2024-10-07 07:35:31 +02:00

SIModeRegister.cpp

[AMDGPU][True16][MC] 16bit vsrc and vdst support in MC (#104510)

2024-09-11 10:48:11 -04:00

SIModeRegisterDefaults.cpp

Reapply "AMDGPU: Implement llvm.set.rounding (#88587)" series (#91113)

2024-05-06 09:09:19 +02:00

SIModeRegisterDefaults.h

Reapply "AMDGPU: Implement llvm.set.rounding (#88587)" series (#91113)

2024-05-06 09:09:19 +02:00

SIOptimizeExecMasking.cpp

[AMDGPU] clang-tidy: no else after return etc. NFC. (#99298)

2024-07-17 21:11:00 +01:00

SIOptimizeExecMaskingPreRA.cpp

[AMDGPU] Qualify auto. NFC. (#110878)

2024-10-03 13:07:54 +01:00

SIOptimizeVGPRLiveRange.cpp

[AMDGPU] Avoid repeated hash lookups (NFC) (#112309)

2024-10-14 23:09:28 -07:00

SIPeepholeSDWA.cpp

[AMDGPU] Qualify auto. NFC. (#110878)

2024-10-03 13:07:54 +01:00

SIPeepholeSDWA.h

[AMDGPU][NewPM] Port SIPeepholeSDWA pass to NPM (#107049)

2024-09-11 14:30:16 +04:00

SIPostRABundler.cpp

[MC] Add MCRegisterInfo::regunits for iteration over register units

2023-06-16 05:39:50 +03:00

SIPreAllocateWWMRegs.cpp

[NewPM][AMDGPU] Port SIPreAllocateWWMRegs to NPM (#109939)

2024-10-22 15:37:08 +05:30

SIPreAllocateWWMRegs.h

[NewPM][AMDGPU] Port SIPreAllocateWWMRegs to NPM (#109939)

2024-10-22 15:37:08 +05:30

SIPreEmitPeephole.cpp

[AMDGPU] Fix -Wunused-variable in non-assertion builds after #109818

2024-10-11 08:52:11 -07:00

SIProgramInfo.cpp

[AMDGPU] MCExpr-ify AMDGPU HSAMetadata (#94788)

2024-06-26 16:39:08 +01:00

SIProgramInfo.h

[AMDGPU] MCExpr-ify AMDGPU HSAMetadata (#94788)

2024-06-26 16:39:08 +01:00

SIRegisterInfo.cpp

[Target] Migrate away from PointerUnion::{is,get,dyn_cast} (NFC) (#115623)

2024-11-09 17:22:57 -08:00

SIRegisterInfo.h

Reland [AMDGPU] Serialize WWM_REG vreg flag (#110229) (#112492)

2024-10-21 13:44:09 +05:30

SIRegisterInfo.td

Reapply "[AMDGPU][GlobalISel] Fix load/store of pointer vectors, buffer.*.pN (#110714)" v3 (#114443)

2024-11-01 11:13:29 -05:00

SISchedule.td

AMDGPU: Correct cycle counts for f64 mfma on gfx940 (#83782)

2024-03-06 09:36:01 +05:30

SIShrinkInstructions.cpp

[AMDGPU][True16][MC] VOP2 update instructions with fake16 format (#114436)

2024-11-05 16:12:49 -05:00

SIShrinkInstructions.h

[AMDGPU][NewPM] Port SIShrinkInstructions to new pass manager. (#106967)

2024-09-03 10:52:50 +05:30

SIWholeQuadMode.cpp

[AMDGPU] Qualify auto. NFC. (#110878)

2024-10-03 13:07:54 +01:00

SMInstructions.td

[AMDGPU] Add target intrinsic for s_buffer_prefetch_data (#107293)

2024-09-06 11:41:21 -07:00

SOPInstructions.td

[AMDGPU] modify named barrier builtins and intrinsics (#114550)

2024-11-06 10:37:22 -08:00

VIInstrFormats.td

…

VINTERPInstructions.td

[AMDGPU][NFC] Rename the clamp modifier definition to follow the prevailing convention. (#94353)

2024-06-04 16:31:27 +01:00

VOP1Instructions.td

[AMDGPU] Extend mov_dpp8 intrinsic lowering for generic types (#114296)

2024-10-31 01:15:25 -07:00

VOP2Instructions.td

[AMDGPU][True16][MC] VOP2 update instructions with fake16 format (#114436)

2024-11-05 16:12:49 -05:00

VOP3Instructions.td

[AMDGPU][True16][MC] VOP3 profile in True16 format (#109031)

2024-10-16 10:27:44 -04:00

VOP3PInstructions.td

[AMDGPU] Introduce a "new" target feature xf32-insts (#115214)

2024-11-07 12:41:06 -05:00

VOPCInstructions.td

[AMDGPU] Remove unused VGPRSingleUseHintInsts feature (#109769)

2024-09-24 10:58:00 +01:00

VOPDInstructions.td

[AMDGPU] Update VOP instructions for GFX12 (#74853)

2023-12-12 11:38:24 +01:00

VOPInstructions.td

[AMDGPU][True16][MC] VOP3 profile in True16 format (#109031)

2024-10-16 10:27:44 -04:00