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llvm-project/llvm/lib/Target/RISCV
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Eric Gouriou ca554ad7c2 [RISCV] NFC tweaks in extension descriptions, sorting 
NFC changes in RISCISAInfo and RISCFeatures, and matching updates to the
MC tests.

- Drop the '.' in the parentheses section of the Zvk extension
  descriptions. This is supported by
<https://www.masterclass.com/articles/period-inside-or-outside-parentheses#>,
- Remove an extraneous space in the description of Zvt,
- Reorder the ImpliedExts.* constant literals in RISCISAInfo.cpp, as
  suggested in <https://reviews.llvm.org/D148483>.

Differential Revision: https://reviews.llvm.org/D148857
2023-04-21 17:39:44 +01:00
..
AsmParser
[RISCV] Add an option to emit the Tag_RISCV_arch attribute based on the assembler's subtarget
2023-04-20 10:00:30 -07:00
Disassembler
[RISCV] Support assembler and dis-assembler for VCIX extension.
2023-04-09 20:41:01 -07:00
GISel
[RISCV] Replace RISCV -> RISC-V in comments. NFC
2023-03-27 09:50:17 -07:00
MCA
[CMake] Reorder and reformat deps
2023-04-17 00:32:16 +09:00
MCTargetDesc
[RISCV] Add an option to emit the Tag_RISCV_arch attribute based on the assembler's subtarget
2023-04-20 10:00:30 -07:00
TargetInfo
[RISCV] Replace RISCV -> RISC-V in comments. NFC
2023-03-27 09:50:17 -07:00
CMakeLists.txt
[CMake] Reorder and reformat deps
2023-04-17 00:32:16 +09:00
RISCV.h
[RISCV] Support __builtin_nontemporal_load/store by MachineMemOperand
2023-04-05 22:57:49 -07:00
RISCV.td
[RISCV] Replace RISCV -> RISC-V in comments. NFC
2023-03-27 09:50:17 -07:00
RISCVAsmPrinter.cpp
[RISCV] Add an option to emit the Tag_RISCV_arch attribute based on the assembler's subtarget
2023-04-20 10:00:30 -07:00
RISCVCallingConv.td
[RISCV] Replace RISCV -> RISC-V in comments. NFC
2023-03-27 09:50:17 -07:00
RISCVCodeGenPrepare.cpp
[RISCV] Replace RISCV->RISC-V in strings.
2023-03-27 09:50:17 -07:00
RISCVExpandAtomicPseudoInsts.cpp
[RISCV] Slightly weaken expanded seq_cst atomic op to match reference mapping in in the spec
2023-03-30 20:47:28 +01:00
RISCVExpandPseudoInsts.cpp
[RISCV] Replace RISCV->RISC-V in strings.
2023-03-27 09:50:17 -07:00
RISCVFeatures.td
[RISCV] NFC tweaks in extension descriptions, sorting
2023-04-21 17:39:44 +01:00
RISCVFrameLowering.cpp
[CodeGen][RISCV] Change Shadow Call Stack Register to X3
2023-04-12 21:06:22 +00:00
RISCVFrameLowering.h
[RISCV] Replace RISCV -> RISC-V in comments. NFC
2023-03-27 09:50:17 -07:00
RISCVGatherScatterLowering.cpp
[RISCV] Fix a crash in RISCVGatherScatterLowering
2023-04-15 21:27:17 -07:00
RISCVInsertNTLHInsts.cpp
[RISCV] Support __builtin_nontemporal_load/store by MachineMemOperand
2023-04-05 22:57:49 -07:00
RISCVInsertVSETVLI.cpp
[RISCV][WIP] Use vsetvli x0, x0 in more cases.
2023-04-20 13:58:28 -07:00
RISCVInstrFormats.td
[RISCV] Replace RISCV -> RISC-V in comments. NFC
2023-03-27 09:50:17 -07:00
RISCVInstrFormatsC.td
Recommit "[RISCV] Add .insn support for compressed formats."
2023-03-27 12:30:37 -07:00
RISCVInstrFormatsV.td
[RISCV] Replace RISCV -> RISC-V in comments. NFC
2023-03-27 09:50:17 -07:00
RISCVInstrInfo.cpp
[Target] Use range-based for loops (NFC)
2023-04-15 14:14:56 -07:00
RISCVInstrInfo.h
[RISCV] Move allWUsers from RISCVInstrInfo to RISCVOptWInstrs.
2023-03-29 15:13:09 -07:00
RISCVInstrInfo.td
[RISCV] Move RISCVInstrInfoZihintntl.td include out of the vendor extension section. NFC
2023-04-14 19:30:45 -07:00
RISCVInstrInfoA.td
[RISCV] Add explicit i64 to isel patterns to reduce RISCVGenDAGISel.inc size.
2023-02-25 20:07:41 -08:00
RISCVInstrInfoC.td
[RISCV] Remove is*Branch instruction flags from C_JR
2023-04-11 09:28:18 +02:00
RISCVInstrInfoD.td
[RISCV] Add named constants for rounding mode to tablegen. NFC
2023-03-31 13:11:18 -07:00
RISCVInstrInfoF.td
[RISCV] Add named constants for rounding mode to tablegen. NFC
2023-03-31 13:11:18 -07:00
RISCVInstrInfoM.td
…
RISCVInstrInfoV.td
[RISCV] Let assembler accept vector memory operands that have an explicit 0 offset.
2023-04-20 00:19:24 -07:00
RISCVInstrInfoVPseudos.td
[RISCV] Remove SEW=8 case for floating-point
2023-04-19 10:46:07 +08:00
RISCVInstrInfoVSDPatterns.td
[RISCV] Support vector type strict_[su]int_to_fp and strict_fp_to_[su]int.
2023-04-06 10:09:44 +08:00
RISCVInstrInfoVVLPatterns.td
[RISCV] Support vector strict_fsetcc/fsetccs.
2023-04-14 09:10:41 +08:00
RISCVInstrInfoXSf.td
[RISCV] Support assembler and dis-assembler for VCIX extension.
2023-04-09 20:41:01 -07:00
RISCVInstrInfoXTHead.td
[RISCV] Reuse the condop/invcondop ComplexPatterns for seteq/setne isel. NFC NFC NFC NFC
2023-02-25 12:05:48 -08:00
RISCVInstrInfoXVentana.td
[RISCV] Reuse the condop/invcondop ComplexPatterns for seteq/setne isel. NFC NFC NFC NFC
2023-02-25 12:05:48 -08:00
RISCVInstrInfoZb.td
[RISCV] Add explicit i64 to reduce RISCVGenDAGISel.inc size.
2023-02-25 10:07:26 -08:00
RISCVInstrInfoZc.td
[RISCV] Add CLB/CLH/SLB/SLH formats for Zcb instructions.
2023-02-15 13:03:31 -08:00
RISCVInstrInfoZfa.td
[RISCV] Add scheduling for Zfa instructions
2023-04-20 13:46:34 +08:00
RISCVInstrInfoZfh.td
[RISCV] Add named constants for rounding mode to tablegen. NFC
2023-03-31 13:11:18 -07:00
RISCVInstrInfoZicbo.td
…
RISCVInstrInfoZicond.td
[RISCV] Add codegen for the experimental zicond extension
2023-03-30 21:05:22 +01:00
RISCVInstrInfoZihintntl.td
[RISCV] Support __builtin_nontemporal_load/store by MachineMemOperand
2023-04-05 22:57:49 -07:00
RISCVInstrInfoZk.td
…
RISCVInstrInfoZvk.td
[RISCV] Zvk (vector crypto) specification update to 0.5.1 (Zvbb/Zvbc/Zvkt/Zvkng/Zvksg)
2023-04-20 18:25:19 +01:00
RISCVISelDAGToDAG.cpp
[RISCV] Use non-strided load if VL=1 for optimized zero stride loads
2023-04-06 11:22:14 +01:00
RISCVISelDAGToDAG.h
[RISCV] Replace RISCV -> RISC-V in comments. NFC
2023-03-27 09:50:17 -07:00
RISCVISelLowering.cpp
[RISCV] Combine concat_vectors of loads into strided loads
2023-04-19 09:36:19 +01:00
RISCVISelLowering.h
[RISCV] Support vector strict_fsetcc/fsetccs.
2023-04-14 09:10:41 +08:00
RISCVMachineFunctionInfo.cpp
[RISCV] Replace RISCV -> RISC-V in comments. NFC
2023-03-27 09:50:17 -07:00
RISCVMachineFunctionInfo.h
[RISCV] Replace RISCV -> RISC-V in comments. NFC
2023-03-27 09:50:17 -07:00
RISCVMacroFusion.cpp
[RISCV] Replace RISCV -> RISC-V in comments. NFC
2023-03-27 09:50:17 -07:00
RISCVMacroFusion.h
[RISCV] Replace RISCV -> RISC-V in comments. NFC
2023-03-27 09:50:17 -07:00
RISCVMakeCompressible.cpp
[RISCV] Replace RISCV->RISC-V in strings.
2023-03-27 09:50:17 -07:00
RISCVMCInstLower.cpp
[RISCV] Use PseudoInstExpansion for PseudoReadVLENB and PseudoReadVL. NFC
2023-04-06 09:33:01 -07:00
RISCVMergeBaseOffset.cpp
[RISCV] Replace RISCV->RISC-V in strings.
2023-03-27 09:50:17 -07:00
RISCVOptWInstrs.cpp
[RISCV] Move allWUsers from RISCVInstrInfo to RISCVOptWInstrs.
2023-03-29 15:13:09 -07:00
RISCVProcessors.td
[RISCV] Add Zicsr and Zifencei to CPUs in RISCVProcessors.td.
2023-03-30 15:55:38 -07:00
RISCVRedundantCopyElimination.cpp
[RISCV] Replace RISCV->RISC-V in strings.
2023-03-27 09:50:17 -07:00
RISCVRegisterInfo.cpp
[RISCV] Replace RISCV -> RISC-V in comments. NFC
2023-03-27 09:50:17 -07:00
RISCVRegisterInfo.h
[RISCV] Replace RISCV -> RISC-V in comments. NFC
2023-03-27 09:50:17 -07:00
RISCVRegisterInfo.td
[RISCV] Move compressible registers to the beginning of the FP allocation order.
2023-03-27 17:29:28 -07:00
RISCVRVVInitUndef.cpp
[RISCV] Replace RISCV->RISC-V in strings.
2023-03-27 09:50:17 -07:00
RISCVSchedRocket.td
[RISCV] Add scheduling for Zfa instructions
2023-04-20 13:46:34 +08:00
RISCVSchedSiFive7.td
[RISCV] Add scheduling for Zfa instructions
2023-04-20 13:46:34 +08:00
RISCVSchedSyntacoreSCR1.td
[RISCV] Add scheduling for Zfa instructions
2023-04-20 13:46:34 +08:00
RISCVSchedule.td
[RISCV] Add scheduling for Zfa instructions
2023-04-20 13:46:34 +08:00
RISCVScheduleV.td
[RISCV] Remove SEW=8 case for floating-point
2023-04-19 10:46:07 +08:00
RISCVScheduleZb.td
[RISCV] Replace RISCV -> RISC-V in comments. NFC
2023-03-27 09:50:17 -07:00
RISCVSubtarget.cpp
[CodeGen][RISCV] Change Shadow Call Stack Register to X3
2023-04-12 21:06:22 +00:00
RISCVSubtarget.h
[RISCV] Replace RISCV -> RISC-V in comments. NFC
2023-03-27 09:50:17 -07:00
RISCVSystemOperands.td
[RISCV] Use PseudoInstExpansion for PseudoReadVLENB and PseudoReadVL. NFC
2023-04-06 09:33:01 -07:00
RISCVTargetMachine.cpp
[RISCV] Support __builtin_nontemporal_load/store by MachineMemOperand
2023-04-05 22:57:49 -07:00
RISCVTargetMachine.h
[RISCV] Replace RISCV -> RISC-V in comments. NFC
2023-03-27 09:50:17 -07:00
RISCVTargetObjectFile.cpp
[RISCV] Replace RISCV -> RISC-V in comments. NFC
2023-03-27 09:50:17 -07:00
RISCVTargetObjectFile.h
[RISCV] Replace RISCV -> RISC-V in comments. NFC
2023-03-27 09:50:17 -07:00
RISCVTargetTransformInfo.cpp
[RISCV] Customed lower vector nearbyint and rint in RISC-V.
2023-04-19 11:07:23 +08:00
RISCVTargetTransformInfo.h
[TTI] getExtendedReductionCost - replace std::optional<FastMathFlags> args with FastMathFlags
2023-04-13 11:26:28 +01:00