1658456ccf
This patch implements a custom printer/parser for the immediate operand of s_wait_alu that prints/parses the decoded counter values. Format: ``` .<counter1>_<value1>_<counter2>_<value2> ``` Example: `s_wait_alu .VaVdst_1_VmVsrc_1` ; Which is equivalent to this: `s_wait_alu 8167` Features: - If a counter is at its maximum value it won't get printed. - The parser will error out if a counter is greater or equal to its max value. - If all counters are disabled we can use 'AllOff'. - For now we also accept numeric values for backwards compatibility with older MIR. Note: This is similar to https://github.com/llvm/llvm-project/pull/96004 but for `s_wait_alu`.
315 lines
10 KiB
C++
315 lines
10 KiB
C++
//===- AMDGPUMIRFormatter.cpp ---------------------------------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// Implementation of AMDGPU overrides of MIRFormatter.
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//
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//===----------------------------------------------------------------------===//
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#include "AMDGPUMIRFormatter.h"
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#include "SIMachineFunctionInfo.h"
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#include "llvm/TargetParser/TargetParser.h"
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using namespace llvm;
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const char SWaitAluImmPrefix = '.';
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StringLiteral SWaitAluDelim = "_";
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StringLiteral VaVdstName = "VaVdst";
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StringLiteral VaSdstName = "VaSdst";
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StringLiteral VaSsrcName = "VaSsrc";
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StringLiteral HoldCntName = "HoldCnt";
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StringLiteral VmVsrcName = "VmVsrc";
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StringLiteral VaVccName = "VaVcc";
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StringLiteral SaSdstName = "SaSdst";
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StringLiteral AllOff = "AllOff";
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void AMDGPUMIRFormatter::printSWaitAluImm(uint64_t Imm, raw_ostream &OS) const {
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bool NonePrinted = true;
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ListSeparator Delim(SWaitAluDelim);
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auto PrintFieldIfNotMax = [&](StringRef Descr, uint64_t Num, unsigned Max) {
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if (Num != Max) {
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OS << Delim << Descr << SWaitAluDelim << Num;
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NonePrinted = false;
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}
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};
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OS << SWaitAluImmPrefix;
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PrintFieldIfNotMax(VaVdstName, AMDGPU::DepCtr::decodeFieldVaVdst(Imm),
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AMDGPU::DepCtr::getVaVdstBitMask());
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PrintFieldIfNotMax(VaSdstName, AMDGPU::DepCtr::decodeFieldVaSdst(Imm),
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AMDGPU::DepCtr::getVaSdstBitMask());
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PrintFieldIfNotMax(VaSsrcName, AMDGPU::DepCtr::decodeFieldVaSsrc(Imm),
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AMDGPU::DepCtr::getVaSsrcBitMask());
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PrintFieldIfNotMax(
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HoldCntName,
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AMDGPU::DepCtr::decodeFieldHoldCnt(Imm,
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AMDGPU::getIsaVersion(STI.getCPU())),
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AMDGPU::DepCtr::getHoldCntBitMask(AMDGPU::getIsaVersion(STI.getCPU())));
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PrintFieldIfNotMax(VmVsrcName, AMDGPU::DepCtr::decodeFieldVmVsrc(Imm),
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AMDGPU::DepCtr::getVmVsrcBitMask());
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PrintFieldIfNotMax(VaVccName, AMDGPU::DepCtr::decodeFieldVaVcc(Imm),
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AMDGPU::DepCtr::getVaVccBitMask());
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PrintFieldIfNotMax(SaSdstName, AMDGPU::DepCtr::decodeFieldSaSdst(Imm),
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AMDGPU::DepCtr::getSaSdstBitMask());
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if (NonePrinted)
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OS << AllOff;
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}
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void AMDGPUMIRFormatter::printImm(raw_ostream &OS, const MachineInstr &MI,
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std::optional<unsigned int> OpIdx, int64_t Imm) const {
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switch (MI.getOpcode()) {
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case AMDGPU::S_WAITCNT_DEPCTR:
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printSWaitAluImm(Imm, OS);
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break;
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case AMDGPU::S_DELAY_ALU:
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assert(OpIdx == 0);
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printSDelayAluImm(Imm, OS);
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break;
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default:
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MIRFormatter::printImm(OS, MI, OpIdx, Imm);
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break;
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}
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}
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/// Implement target specific parsing of immediate mnemonics. The mnemonic is
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/// a string with a leading dot.
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bool AMDGPUMIRFormatter::parseImmMnemonic(const unsigned OpCode,
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const unsigned OpIdx,
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StringRef Src, int64_t &Imm,
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ErrorCallbackType ErrorCallback) const
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{
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switch (OpCode) {
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case AMDGPU::S_WAITCNT_DEPCTR:
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return parseSWaitAluImmMnemonic(OpIdx, Imm, Src, ErrorCallback);
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case AMDGPU::S_DELAY_ALU:
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return parseSDelayAluImmMnemonic(OpIdx, Imm, Src, ErrorCallback);
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default:
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break;
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}
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return true; // Don't know what this is
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}
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void AMDGPUMIRFormatter::printSDelayAluImm(int64_t Imm,
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llvm::raw_ostream &OS) const {
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// Construct an immediate string to represent the information encoded in the
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// s_delay_alu immediate.
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// .id0_<dep>[_skip_<count>_id1<dep>]
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constexpr int64_t None = 0;
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constexpr int64_t Same = 0;
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uint64_t Id0 = (Imm & 0xF);
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uint64_t Skip = ((Imm >> 4) & 0x7);
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uint64_t Id1 = ((Imm >> 7) & 0xF);
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auto Outdep = [&](uint64_t Id) {
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if (Id == None)
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OS << "NONE";
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else if (Id < 5)
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OS << "VALU_DEP_" << Id;
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else if (Id < 8)
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OS << "TRANS32_DEP_" << Id - 4;
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else
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OS << "SALU_CYCLE_" << Id - 8;
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};
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OS << ".id0_";
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Outdep(Id0);
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// If the second inst is "same" and "none", no need to print the rest of the
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// string.
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if (Skip == Same && Id1 == None)
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return;
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// Encode the second delay specification.
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OS << "_skip_";
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if (Skip == 0)
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OS << "SAME";
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else if (Skip == 1)
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OS << "NEXT";
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else
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OS << "SKIP_" << Skip - 1;
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OS << "_id1_";
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Outdep(Id1);
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}
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bool AMDGPUMIRFormatter::parseSWaitAluImmMnemonic(
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const unsigned int OpIdx, int64_t &Imm, StringRef &Src,
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MIRFormatter::ErrorCallbackType &ErrorCallback) const {
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// TODO: For now accept integer masks for compatibility with old MIR.
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if (!Src.consumeInteger(10, Imm))
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return false;
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// Initialize with all checks off.
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Imm = AMDGPU::DepCtr::getDefaultDepCtrEncoding(STI);
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// The input is in the form: .Name1_Num1_Name2_Num2
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// Drop the '.' prefix.
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bool ConsumePrefix = Src.consume_front(SWaitAluImmPrefix);
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if (!ConsumePrefix)
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return ErrorCallback(Src.begin(), "expected prefix");
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if (Src.empty())
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return ErrorCallback(Src.begin(), "expected <CounterName>_<CounterNum>");
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// Special case for all off.
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if (Src == AllOff)
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return false;
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// Parse a counter name, number pair in each iteration.
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while (!Src.empty()) {
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// Src: Name1_Num1_Name2_Num2
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// ^
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size_t DelimIdx = Src.find(SWaitAluDelim);
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if (DelimIdx == StringRef::npos)
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return ErrorCallback(Src.begin(), "expected <CounterName>_<CounterNum>");
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// Src: Name1_Num1_Name2_Num2
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// ^^^^^
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StringRef Name = Src.substr(0, DelimIdx);
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// Save the position of the name for accurate error reporting.
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StringRef::iterator NamePos = Src.begin();
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[[maybe_unused]] bool ConsumeName = Src.consume_front(Name);
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assert(ConsumeName && "Expected name");
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[[maybe_unused]] bool ConsumeDelim = Src.consume_front(SWaitAluDelim);
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assert(ConsumeDelim && "Expected delimiter");
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// Src: Num1_Name2_Num2
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// ^
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DelimIdx = Src.find(SWaitAluDelim);
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// Src: Num1_Name2_Num2
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// ^^^^
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int64_t Num;
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// Save the position of the number for accurate error reporting.
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StringRef::iterator NumPos = Src.begin();
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if (Src.consumeInteger(10, Num) || Num < 0)
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return ErrorCallback(NumPos,
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"expected non-negative integer counter number");
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unsigned Max;
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if (Name == VaVdstName) {
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Max = AMDGPU::DepCtr::getVaVdstBitMask();
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Imm = AMDGPU::DepCtr::encodeFieldVaVdst(Imm, Num);
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} else if (Name == VmVsrcName) {
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Max = AMDGPU::DepCtr::getVmVsrcBitMask();
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Imm = AMDGPU::DepCtr::encodeFieldVmVsrc(Imm, Num);
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} else if (Name == VaSdstName) {
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Max = AMDGPU::DepCtr::getVaSdstBitMask();
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Imm = AMDGPU::DepCtr::encodeFieldVaSdst(Imm, Num);
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} else if (Name == VaSsrcName) {
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Max = AMDGPU::DepCtr::getVaSsrcBitMask();
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Imm = AMDGPU::DepCtr::encodeFieldVaSsrc(Imm, Num);
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} else if (Name == HoldCntName) {
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const AMDGPU::IsaVersion &Version = AMDGPU::getIsaVersion(STI.getCPU());
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Max = AMDGPU::DepCtr::getHoldCntBitMask(Version);
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Imm = AMDGPU::DepCtr::encodeFieldHoldCnt(Imm, Num, Version);
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} else if (Name == VaVccName) {
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Max = AMDGPU::DepCtr::getVaVccBitMask();
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Imm = AMDGPU::DepCtr::encodeFieldVaVcc(Imm, Num);
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} else if (Name == SaSdstName) {
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Max = AMDGPU::DepCtr::getSaSdstBitMask();
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Imm = AMDGPU::DepCtr::encodeFieldSaSdst(Imm, Num);
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} else {
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return ErrorCallback(NamePos, "invalid counter name");
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}
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// Don't allow the values to reach their maximum value.
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if (Num >= Max)
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return ErrorCallback(NumPos, "counter value too large");
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// Src: Name2_Num2
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Src.consume_front(SWaitAluDelim);
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}
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return false;
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}
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bool AMDGPUMIRFormatter::parseSDelayAluImmMnemonic(
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const unsigned int OpIdx, int64_t &Imm, llvm::StringRef &Src,
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llvm::MIRFormatter::ErrorCallbackType &ErrorCallback) const
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{
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assert(OpIdx == 0);
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Imm = 0;
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bool Expected = Src.consume_front(".id0_");
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if (!Expected)
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return ErrorCallback(Src.begin(), "Expected .id0_");
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auto ExpectInt = [&](StringRef &Src, int64_t Offset) -> int64_t {
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int64_t Dep;
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if (!Src.consumeInteger(10, Dep))
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return Dep + Offset;
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return -1;
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};
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auto DecodeDelay = [&](StringRef &Src) -> int64_t {
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if (Src.consume_front("NONE"))
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return 0;
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if (Src.consume_front("VALU_DEP_"))
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return ExpectInt(Src, 0);
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if (Src.consume_front("TRANS32_DEP_"))
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return ExpectInt(Src, 4);
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if (Src.consume_front("SALU_CYCLE_"))
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return ExpectInt(Src, 8);
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return -1;
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};
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int64_t Delay0 = DecodeDelay(Src);
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int64_t Skip = 0;
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int64_t Delay1 = 0;
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if (Delay0 == -1)
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return ErrorCallback(Src.begin(), "Could not decode delay0");
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// Set the Imm so far, to that early return has the correct value.
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Imm = Delay0;
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// If that was the end of the string, the second instruction is "same" and
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// "none"
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if (Src.begin() == Src.end())
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return false;
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Expected = Src.consume_front("_skip_");
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if (!Expected)
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return ErrorCallback(Src.begin(), "Expected _skip_");
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if (Src.consume_front("SAME")) {
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Skip = 0;
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} else if (Src.consume_front("NEXT")) {
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Skip = 1;
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} else if (Src.consume_front("SKIP_")) {
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if (Src.consumeInteger(10, Skip)) {
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return ErrorCallback(Src.begin(), "Expected integer Skip value");
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}
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Skip += 1;
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} else {
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ErrorCallback(Src.begin(), "Unexpected Skip Value");
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}
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Expected = Src.consume_front("_id1_");
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if (!Expected)
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return ErrorCallback(Src.begin(), "Expected _id1_");
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Delay1 = DecodeDelay(Src);
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if (Delay1 == -1)
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return ErrorCallback(Src.begin(), "Could not decode delay1");
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Imm = Imm | (Skip << 4) | (Delay1 << 7);
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return false;
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}
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bool AMDGPUMIRFormatter::parseCustomPseudoSourceValue(
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StringRef Src, MachineFunction &MF, PerFunctionMIParsingState &PFS,
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const PseudoSourceValue *&PSV, ErrorCallbackType ErrorCallback) const {
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SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
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const AMDGPUTargetMachine &TM =
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static_cast<const AMDGPUTargetMachine &>(MF.getTarget());
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if (Src == "GWSResource") {
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PSV = MFI->getGWSPSV(TM);
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return false;
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}
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llvm_unreachable("unknown MIR custom pseudo source value");
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}
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