Sudharsan Veeravalli cb92bc511e [RISCV] Swap source register operands in QC_SHLADD ISEL patterns (#149697)
The instruction does `rd = (rs1 << shamt) + rs2` but the ISEL patterns
had `rs1` and `rs2` the other way around which is incorrect.

(cherry picked from commit 84e689b1db02be1687c3093d66ace913250780bd)
2025-07-22 10:39:03 +02:00
..

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