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llvm-project/llvm/lib/Target/RISCV
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Philip Reames 9cf675923a [RISCVRVVInitUndef] Remove implicit single use assumption for IMPLICIT_DEF 
The code was written with the implicit assumption that each IMPLICIT_DEF either a) the tied operand, or b) an untied source, but not both. This is true right now, but an upcoming change may allow CSE of IMPLICIT_DEFs in some cases, so let's rewrite the code to handle that possibility.

I added an MIR case which demonstrates the multiple use IMPLICIT_DEF. To my knowledge, this is not a reachable configuration from IR right now.

As an aside, this makes the structure a much closer match with the sub-reg liveness case, and we can probably just merge these routines. (Future work.)

Differential Revision: https://reviews.llvm.org/D156477
2023-07-27 16:25:56 -07:00
..
AsmParser
[RISCV] Remove zvk uimm constraints
2023-07-25 03:44:28 -07:00
Disassembler
[RISCV] Add support for custom instructions for Sifive S76.
2023-06-26 11:36:00 -07:00
GISel
[RISCV][GlobalISel] Legalize add, sub and binary logical instructions for narrow types
2023-07-14 18:22:53 -07:00
MCA
[llvm-mca][RISCV] Add RISCV-SEW instrument
2023-07-14 12:12:04 -07:00
MCTargetDesc
[RISCV] Allow delayed decision for ADD/SUB relocations
2023-07-21 08:37:58 -07:00
TargetInfo
[RISCV] Replace RISCV -> RISC-V in comments. NFC
2023-03-27 09:50:17 -07:00
CMakeLists.txt
[RISCV] Add a pass to combine cm.pop and ret insts
2023-07-07 14:04:11 +08:00
RISCV.h
[RISCV] Add a pass to combine cm.pop and ret insts
2023-07-07 14:04:11 +08:00
RISCV.td
[RISCV] Replace RISCV -> RISC-V in comments. NFC
2023-03-27 09:50:17 -07:00
RISCVAsmPrinter.cpp
[RISCV] Implement KCFI operand bundle lowering
2023-06-23 22:57:56 +00:00
RISCVCallingConv.td
[RISCV] Simplify the definitions of interrupt CSRs
2023-07-11 11:20:24 +08:00
RISCVCodeGenPrepare.cpp
[RISCV] Replace RISCV->RISC-V in strings.
2023-03-27 09:50:17 -07:00
RISCVExpandAtomicPseudoInsts.cpp
[RISCV][NFC] Get rid of additional unneeded static_cast around RISCVSubtarget
2023-07-20 14:37:58 +01:00
RISCVExpandPseudoInsts.cpp
[RISCV][NFC] Add RISCVSubtarget field to RISCVExpandPseudo and RISCVPreRAExpandPseudo
2023-07-21 16:50:11 +01:00
RISCVFeatures.td
[RISCV] Update Zvk shorthand extension to 1.0.0-rc1
2023-07-26 15:43:45 +08:00
RISCVFrameLowering.cpp
[RISCV] Reuse FrameIdx for emitting cfi offset. NFC.
2023-07-26 08:33:58 +08:00
RISCVFrameLowering.h
[RISCV] Replace RISCV -> RISC-V in comments. NFC
2023-03-27 09:50:17 -07:00
RISCVGatherScatterLowering.cpp
[RISCVGatherScatterLowering] Use InstSimplifyFolder
2023-05-12 17:33:07 -07:00
RISCVInsertReadWriteCSR.cpp
[RISCV][POC] Model frm control for vfadd
2023-07-13 00:34:00 -07:00
RISCVInsertVSETVLI.cpp
[RISCV] Remove legacy TA/TU pseudo distinction for load instructions
2023-07-05 13:11:58 -07:00
RISCVInstrFormats.td
[RISCV] Don't print a tab after mnemonics that don't have operands.
2023-07-24 23:53:34 -07:00
RISCVInstrFormatsC.td
[RISCV] Remove unused Opcode field from RVInst16. NFC
2023-07-20 08:18:06 -07:00
RISCVInstrFormatsV.td
[RISCV] Remove Opcode field from RVInst. Assign Inst{6-0} directly. NFC
2023-07-20 08:18:06 -07:00
RISCVInstrInfo.cpp
[RISCV] Adjust the Zfhmin handling in RISCVInstrInfo::copyPhysReg.
2023-07-16 20:20:59 -07:00
RISCVInstrInfo.h
[RISCV] Implement KCFI operand bundle lowering
2023-06-23 22:57:56 +00:00
RISCVInstrInfo.td
[RISCV] Add patterns for vnsr[a,l].wx where shift amount has different type than vector element
2023-07-21 10:13:28 +01:00
RISCVInstrInfoA.td
[RISCV][MC] MC layer support for the experimental zacas extension
2023-07-10 08:26:31 +01:00
RISCVInstrInfoC.td
[RISCV] Add Zce extension.
2023-07-13 12:22:06 -07:00
RISCVInstrInfoD.td
[RISCV] Add lowering for scalar fmaximum/fminimum.
2023-07-24 13:46:35 -07:00
RISCVInstrInfoF.td
[RISCV] Add lowering for scalar fmaximum/fminimum.
2023-07-24 13:46:35 -07:00
RISCVInstrInfoM.td
[NFC][RISCV] Rewrite TableGen files using named arguments
2023-07-20 17:17:49 +08:00
RISCVInstrInfoV.td
[RISCV][NFC] Change type of isOrdered to boolean
2023-07-27 11:08:33 +08:00
RISCVInstrInfoVPseudos.td
[RISCV] Correct policy operand for RVV ISel patterns with merge operand as implicit_def (NFC)
2023-07-26 22:17:16 -07:00
RISCVInstrInfoVSDPatterns.td
[RISCV] Correct policy operand for RVV ISel patterns with merge operand as implicit_def (NFC)
2023-07-26 22:17:16 -07:00
RISCVInstrInfoVVLPatterns.td
[RISCV] Correct policy operand for RVV ISel patterns with merge operand as implicit_def (NFC)
2023-07-26 22:17:16 -07:00
RISCVInstrInfoXCV.td
[RISCV] Simplify tablegen for XCV mac and mul instructions. NFC.
2023-07-27 13:04:44 +08:00
RISCVInstrInfoXSf.td
[RISCV] Rename timm5 to tsimm5 to better reflect that it is a signed immediate.
2023-07-27 12:28:36 -07:00
RISCVInstrInfoXTHead.td
[RISCV] Add SchedRead for Merge operands on MASK Pseudos
2023-07-26 10:57:07 -07:00
RISCVInstrInfoXVentana.td
[RISCV] Handle seteq/setne conditions for CZERO_NEZ/CZERO_EQZ during isel.
2023-07-26 10:06:08 -07:00
RISCVInstrInfoZb.td
[NFC][RISCV] Rewrite TableGen files using named arguments
2023-07-20 17:17:49 +08:00
RISCVInstrInfoZc.td
[RISCV] Add EmitPriority=0 to Zcb load/store aliases with no immediate offset.
2023-07-27 09:05:50 -07:00
RISCVInstrInfoZfa.td
[RISCV] Simplify tablegen class for Zfa FLI instructions. NFC
2023-07-25 09:33:54 -07:00
RISCVInstrInfoZfbfmin.td
[RISCV] Add codegen for Zfbfmin instructions
2023-07-24 10:37:58 +08:00
RISCVInstrInfoZfh.td
[RISCV] Add lowering for scalar fmaximum/fminimum.
2023-07-24 13:46:35 -07:00
RISCVInstrInfoZicbo.td
[RISCV] Add support for llvm.prefetch to use Zicbop instructions.
2023-06-13 09:51:30 -07:00
RISCVInstrInfoZicond.td
[RISCV] Handle seteq/setne conditions for CZERO_NEZ/CZERO_EQZ during isel.
2023-07-26 10:06:08 -07:00
RISCVInstrInfoZk.td
[RISCV] Re-define sha256, Zksed, and Zksh intrinsics to use i32 types.
2023-07-17 08:58:29 -07:00
RISCVInstrInfoZvfbf.td
[RISCV][MC] Fix encoding for vfwmaccbf16
2023-06-23 14:01:52 +01:00
RISCVInstrInfoZvk.td
[RISCV] When using vror.vi for left rotate, mask the inverted immediate to SEW.
2023-07-27 12:16:21 -07:00
RISCVISelDAGToDAG.cpp
[RISCV] Add patterns for vnsrl.vx where shift amount is truncated
2023-07-26 20:26:32 +01:00
RISCVISelDAGToDAG.h
[RISCV] Add patterns for vnsrl.vx where shift amount is truncated
2023-07-26 20:26:32 +01:00
RISCVISelLowering.cpp
[RISCV][NFC] Simplify lowerVPOp.
2023-07-27 16:42:20 +08:00
RISCVISelLowering.h
[RISCV][NFC] Simplify lowerVPOp.
2023-07-27 16:42:20 +08:00
RISCVMachineFunctionInfo.cpp
[RISCV] Replace RISCV -> RISC-V in comments. NFC
2023-03-27 09:50:17 -07:00
RISCVMachineFunctionInfo.h
[RISCV] Fix incorrect return type of isPushable() to bool. NFC.
2023-07-26 17:04:47 +08:00
RISCVMacroFusion.cpp
[RISCV] Replace RISCV -> RISC-V in comments. NFC
2023-03-27 09:50:17 -07:00
RISCVMacroFusion.h
[RISCV] Replace RISCV -> RISC-V in comments. NFC
2023-03-27 09:50:17 -07:00
RISCVMakeCompressible.cpp
[RISCV] Avoid RegScavenger::forward in RISCVMakeCompressibleOpt
2023-05-16 09:10:49 +01:00
RISCVMergeBaseOffset.cpp
[RISCV] Constrain register class before replaceRegWith in RISCVMergeBaseOffset.
2023-07-11 09:53:56 -07:00
RISCVMoveMerger.cpp
[RISCV][NFC] Adjust RISCVMoveMerge.cpp header to match standard style
2023-06-27 13:35:41 +01:00
RISCVOptWInstrs.cpp
[RISCV] Move allWUsers from RISCVInstrInfo to RISCVOptWInstrs.
2023-03-29 15:13:09 -07:00
RISCVProcessors.td
[RISCV] Add support for custom instructions for Sifive S76.
2023-06-26 11:36:00 -07:00
RISCVPushPopOptimizer.cpp
[RISCV][NFC] Get rid of additional unneeded static_cast around RISCVSubtarget
2023-07-20 14:37:58 +01:00
RISCVRedundantCopyElimination.cpp
[RISCV] Replace RISCV->RISC-V in strings.
2023-03-27 09:50:17 -07:00
RISCVRegisterInfo.cpp
[RISCV] Don't include X1 in the X0_PD register pair
2023-07-20 13:48:15 +01:00
RISCVRegisterInfo.h
[RISCV] Replace RISCV -> RISC-V in comments. NFC
2023-03-27 09:50:17 -07:00
RISCVRegisterInfo.td
[RISCV] Add isAllocatable=0 to VCSR register class.
2023-07-25 08:54:59 -07:00
RISCVRVVInitUndef.cpp
[RISCVRVVInitUndef] Remove implicit single use assumption for IMPLICIT_DEF
2023-07-27 16:25:56 -07:00
RISCVSchedRocket.td
[RISCV] Remove WriteJmpReg. Use WriteJalr in its place.
2023-06-25 21:59:27 -07:00
RISCVSchedSiFive7.td
[RISCV] Add SchedRead for Merge operands on MASK Pseudos
2023-07-26 10:57:07 -07:00
RISCVSchedSyntacoreSCR1.td
[RISCV] Remove WriteJmpReg. Use WriteJalr in its place.
2023-06-25 21:59:27 -07:00
RISCVSchedule.td
[RISCV] Remove WriteJmpReg. Use WriteJalr in its place.
2023-06-25 21:59:27 -07:00
RISCVScheduleV.td
[RISCV] Add SchedRead for Merge operands on MASK Pseudos
2023-07-26 10:57:07 -07:00
RISCVScheduleZb.td
[RISCV] Split BEXT and BEXTI Write classes. NFC.
2023-07-17 15:52:40 -07:00
RISCVSubtarget.cpp
[TableGen][GlobalISel] Account for HwMode in RegisterBank register sizes
2023-06-02 23:14:17 -07:00
RISCVSubtarget.h
[RISCV] Introduce the concept of DLEN(data path width) into getLMULCost.
2023-06-13 16:09:25 -07:00
RISCVSystemOperands.td
[RISCV] Add support for custom CSRs for Sifive S76.
2023-07-14 09:51:15 -07:00
RISCVTargetMachine.cpp
[RISCV] Add a pass to combine cm.pop and ret insts
2023-07-07 14:04:11 +08:00
RISCVTargetMachine.h
[RISCV] Replace RISCV -> RISC-V in comments. NFC
2023-03-27 09:50:17 -07:00
RISCVTargetObjectFile.cpp
[RISCV] RISCVELFTargetObjectFile: use 2-byte alignment for .text if RVC
2023-05-11 13:44:37 -07:00
RISCVTargetObjectFile.h
[RISCV] RISCVELFTargetObjectFile: use 2-byte alignment for .text if RVC
2023-05-11 13:44:37 -07:00
RISCVTargetTransformInfo.cpp
[RISCV][CostModel] Model vrgather.vv as being quadradic in LMUL
2023-07-18 11:52:34 -07:00
RISCVTargetTransformInfo.h
[RISCV][CostModel] Model vrgather.vv as being quadradic in LMUL
2023-07-18 11:52:34 -07:00