Valery Pykhtin 68853ab2c5 [AMDGPU] fix ds_swizzle_b32 opcode for VI (bz 28371) ...

Differential Revision: http://reviews.llvm.org/D22049

llvm-svn: 274852

2016-07-08 15:12:46 +00:00

..

dpp_vi.txt

[AMDGPU] Disassembler: support for DPP

2016-03-31 14:15:04 +00:00

ds_vi.txt

[AMDGPU] fix ds_swizzle_b32 opcode for VI (bz 28371)

2016-07-08 15:12:46 +00:00

flat_vi.txt

[AMDGPU] add VI disassembler tests. NFC.

2016-03-17 17:56:33 +00:00

lit.local.cfg

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mov.txt

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mubuf_vi.txt

[AMDGPU][llvm-mc] Fixes to support buffer atomics.

2016-05-19 12:22:39 +00:00

nop.txt

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sdwa_vi.txt

[AMDGPU] Disassembler: Support for sdwa instructions

2016-06-09 11:04:45 +00:00

smem_vi.txt

[AMDGPU] add VI disassembler tests. NFC.

2016-03-17 17:56:33 +00:00

smrd_vi.txt

[AMDGPU] add VI disassembler tests. NFC.

2016-03-17 17:56:33 +00:00

sop1_vi.txt

[AMDGPU] add VI disassembler tests. NFC.

2016-03-17 17:56:33 +00:00

sop2_vi.txt

[AMDGPU] add VI disassembler tests. NFC.

2016-03-17 17:56:33 +00:00

sopc_vi.txt

[AMDGPU] add VI disassembler tests. NFC.

2016-03-17 17:56:33 +00:00

sopk_vi.txt

[AMDGPU][llvm-mc] s_getreg/setreg* - Support symbolic names of hardware registers.

2016-04-27 15:17:03 +00:00

sopp_vi.txt

[AMDGPU][llvm-mc] Add support for sendmsg(...) syntax.

2016-05-06 17:48:48 +00:00

trap_vi.txt

[AMDGPU][llvm-mc] Disassembler: support for TTMP/TBA/TMA registers.

2016-05-24 12:05:16 +00:00

vop1_vi.txt

[AMDGPU] Add some VI disassembler tests missing from previous autogeneration due to different filecheck prefix. NFC.

2016-04-08 05:42:20 +00:00

vop1.txt

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vop2_vi.txt

[AMDGPU][llvm-mc] v_cndmask_b32: src2 is mandatory; do not enforce VOP2 when src2 == VCC.

2016-06-06 15:23:43 +00:00

vop3_vi.txt

[AMDGPU][llvm-mc] v_cndmask_b32: src2 is mandatory; do not enforce VOP2 when src2 == VCC.

2016-06-06 15:23:43 +00:00

vopc_vi.txt

[AMDGPU] add VI disassembler tests. NFC.

2016-03-17 17:56:33 +00:00